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c2fb3b33f2
we are now infering number of IRQ lines based on correct compatible flag, which renders this binding completely useless. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
299 lines
6.1 KiB
Plaintext
299 lines
6.1 KiB
Plaintext
/*
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* Device Tree Source for OMAP2 SoC
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*
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* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/pinctrl/omap.h>
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#include "skeleton.dtsi"
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/ {
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compatible = "ti,omap2430", "ti,omap2420", "ti,omap2";
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interrupt-parent = <&intc>;
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aliases {
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serial0 = &uart1;
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serial1 = &uart2;
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serial2 = &uart3;
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i2c0 = &i2c1;
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i2c1 = &i2c2;
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};
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cpus {
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#address-cells = <0>;
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#size-cells = <0>;
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cpu {
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compatible = "arm,arm1136jf-s";
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device_type = "cpu";
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};
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};
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pmu {
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compatible = "arm,arm1136-pmu";
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interrupts = <3>;
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};
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soc {
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compatible = "ti,omap-infra";
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mpu {
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compatible = "ti,omap2-mpu";
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ti,hwmods = "mpu";
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};
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};
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ocp {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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ti,hwmods = "l3_main";
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aes: aes@480a6000 {
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compatible = "ti,omap2-aes";
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ti,hwmods = "aes";
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reg = <0x480a6000 0x50>;
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dmas = <&sdma 9 &sdma 10>;
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dma-names = "tx", "rx";
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};
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hdq1w: 1w@480b2000 {
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compatible = "ti,omap2420-1w";
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ti,hwmods = "hdq1w";
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reg = <0x480b2000 0x1000>;
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interrupts = <58>;
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};
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intc: interrupt-controller@1 {
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compatible = "ti,omap2-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x480FE000 0x1000>;
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};
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sdma: dma-controller@48056000 {
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compatible = "ti,omap2430-sdma", "ti,omap2420-sdma";
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ti,hwmods = "dma";
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reg = <0x48056000 0x1000>;
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interrupts = <12>,
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<13>,
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<14>,
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<15>;
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#dma-cells = <1>;
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#dma-channels = <32>;
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#dma-requests = <64>;
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};
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i2c1: i2c@48070000 {
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compatible = "ti,omap2-i2c";
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ti,hwmods = "i2c1";
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reg = <0x48070000 0x80>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <56>;
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dmas = <&sdma 27 &sdma 28>;
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dma-names = "tx", "rx";
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};
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i2c2: i2c@48072000 {
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compatible = "ti,omap2-i2c";
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ti,hwmods = "i2c2";
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reg = <0x48072000 0x80>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <57>;
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dmas = <&sdma 29 &sdma 30>;
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dma-names = "tx", "rx";
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};
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mcspi1: mcspi@48098000 {
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compatible = "ti,omap2-mcspi";
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ti,hwmods = "mcspi1";
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reg = <0x48098000 0x100>;
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interrupts = <65>;
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dmas = <&sdma 35 &sdma 36 &sdma 37 &sdma 38
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&sdma 39 &sdma 40 &sdma 41 &sdma 42>;
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dma-names = "tx0", "rx0", "tx1", "rx1",
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"tx2", "rx2", "tx3", "rx3";
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};
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mcspi2: mcspi@4809a000 {
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compatible = "ti,omap2-mcspi";
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ti,hwmods = "mcspi2";
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reg = <0x4809a000 0x100>;
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interrupts = <66>;
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dmas = <&sdma 43 &sdma 44 &sdma 45 &sdma 46>;
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dma-names = "tx0", "rx0", "tx1", "rx1";
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};
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rng: rng@480a0000 {
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compatible = "ti,omap2-rng";
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ti,hwmods = "rng";
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reg = <0x480a0000 0x50>;
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interrupts = <52>;
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};
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sham: sham@480a4000 {
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compatible = "ti,omap2-sham";
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ti,hwmods = "sham";
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reg = <0x480a4000 0x64>;
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interrupts = <51>;
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dmas = <&sdma 13>;
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dma-names = "rx";
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};
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uart1: serial@4806a000 {
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compatible = "ti,omap2-uart";
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ti,hwmods = "uart1";
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reg = <0x4806a000 0x2000>;
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interrupts = <72>;
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dmas = <&sdma 49 &sdma 50>;
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dma-names = "tx", "rx";
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clock-frequency = <48000000>;
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};
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uart2: serial@4806c000 {
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compatible = "ti,omap2-uart";
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ti,hwmods = "uart2";
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reg = <0x4806c000 0x400>;
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interrupts = <73>;
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dmas = <&sdma 51 &sdma 52>;
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dma-names = "tx", "rx";
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clock-frequency = <48000000>;
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};
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uart3: serial@4806e000 {
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compatible = "ti,omap2-uart";
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ti,hwmods = "uart3";
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reg = <0x4806e000 0x400>;
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interrupts = <74>;
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dmas = <&sdma 53 &sdma 54>;
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dma-names = "tx", "rx";
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clock-frequency = <48000000>;
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};
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timer2: timer@4802a000 {
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compatible = "ti,omap2420-timer";
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reg = <0x4802a000 0x400>;
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interrupts = <38>;
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ti,hwmods = "timer2";
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};
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timer3: timer@48078000 {
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compatible = "ti,omap2420-timer";
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reg = <0x48078000 0x400>;
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interrupts = <39>;
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ti,hwmods = "timer3";
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};
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timer4: timer@4807a000 {
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compatible = "ti,omap2420-timer";
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reg = <0x4807a000 0x400>;
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interrupts = <40>;
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ti,hwmods = "timer4";
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};
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timer5: timer@4807c000 {
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compatible = "ti,omap2420-timer";
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reg = <0x4807c000 0x400>;
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interrupts = <41>;
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ti,hwmods = "timer5";
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ti,timer-dsp;
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};
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timer6: timer@4807e000 {
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compatible = "ti,omap2420-timer";
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reg = <0x4807e000 0x400>;
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interrupts = <42>;
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ti,hwmods = "timer6";
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ti,timer-dsp;
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};
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timer7: timer@48080000 {
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compatible = "ti,omap2420-timer";
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reg = <0x48080000 0x400>;
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interrupts = <43>;
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ti,hwmods = "timer7";
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ti,timer-dsp;
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};
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timer8: timer@48082000 {
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compatible = "ti,omap2420-timer";
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reg = <0x48082000 0x400>;
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interrupts = <44>;
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ti,hwmods = "timer8";
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ti,timer-dsp;
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};
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timer9: timer@48084000 {
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compatible = "ti,omap2420-timer";
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reg = <0x48084000 0x400>;
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interrupts = <45>;
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ti,hwmods = "timer9";
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ti,timer-pwm;
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};
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timer10: timer@48086000 {
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compatible = "ti,omap2420-timer";
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reg = <0x48086000 0x400>;
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interrupts = <46>;
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ti,hwmods = "timer10";
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ti,timer-pwm;
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};
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timer11: timer@48088000 {
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compatible = "ti,omap2420-timer";
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reg = <0x48088000 0x400>;
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interrupts = <47>;
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ti,hwmods = "timer11";
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ti,timer-pwm;
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};
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timer12: timer@4808a000 {
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compatible = "ti,omap2420-timer";
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reg = <0x4808a000 0x400>;
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interrupts = <48>;
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ti,hwmods = "timer12";
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ti,timer-pwm;
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};
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dss: dss@48050000 {
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compatible = "ti,omap2-dss";
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reg = <0x48050000 0x400>;
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status = "disabled";
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ti,hwmods = "dss_core";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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dispc@48050400 {
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compatible = "ti,omap2-dispc";
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reg = <0x48050400 0x400>;
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interrupts = <25>;
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ti,hwmods = "dss_dispc";
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};
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rfbi: encoder@48050800 {
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compatible = "ti,omap2-rfbi";
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reg = <0x48050800 0x400>;
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status = "disabled";
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ti,hwmods = "dss_rfbi";
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};
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venc: encoder@48050c00 {
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compatible = "ti,omap2-venc";
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reg = <0x48050c00 0x400>;
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status = "disabled";
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ti,hwmods = "dss_venc";
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};
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};
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};
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};
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