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e76e9aebcd
As a quick hack we make the old intel_gtt structure mutable so we can fool a bunch of the existing code which depends on elements in that data structure. We can/should try to remove this in a subsequent patch. This should preserve the old gtt init behavior which upon writing these patches seems incorrect. The next patch will fix these things. The one exception is VLV which doesn't have the preserved flush control write behavior. Since we want to do that for all GEN6+ stuff, we'll handle that in a later patch. Mainstream VLV support doesn't actually exist yet anyway. v2: Update the comment to remove the "voodoo" Check that the last pte written matches what we readback v3: actually kill cache_level_to_agp_type since most of the flags will disappear in an upcoming patch v4: v3 was actually not what we wanted (Daniel) Make the ggtt bind assertions better and stricter (Chris) Fix some uncaught errors at gtt init (Chris) Some other random stuff that Chris wanted v5: check for i==0 in gen6_ggtt_bind_object to shut up gcc (Ben) Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Reviewed-by [v4]: Chris Wilson <chris@chris-wilson.co.uk> [danvet: Make the cache_level -> agp_flags conversion for pre-gen6 a tad more robust by mapping everything != CACHE_NONE to the cached agp flag - we have a 1:1 uncached mapping, but different modes of cacheable (at least on later generations). Suggested by Chris Wilson.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
55 lines
1.6 KiB
C
55 lines
1.6 KiB
C
/* Common header for intel-gtt.ko and i915.ko */
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#ifndef _DRM_INTEL_GTT_H
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#define _DRM_INTEL_GTT_H
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struct intel_gtt {
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/* Size of memory reserved for graphics by the BIOS */
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unsigned int stolen_size;
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/* Total number of gtt entries. */
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unsigned int gtt_total_entries;
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/* Part of the gtt that is mappable by the cpu, for those chips where
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* this is not the full gtt. */
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unsigned int gtt_mappable_entries;
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/* Whether i915 needs to use the dmar apis or not. */
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unsigned int needs_dmar : 1;
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/* Whether we idle the gpu before mapping/unmapping */
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unsigned int do_idle_maps : 1;
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/* Share the scratch page dma with ppgtts. */
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dma_addr_t scratch_page_dma;
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struct page *scratch_page;
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/* for ppgtt PDE access */
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u32 __iomem *gtt;
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/* needed for ioremap in drm/i915 */
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phys_addr_t gma_bus_addr;
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} *intel_gtt_get(void);
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int intel_gmch_probe(struct pci_dev *bridge_pdev, struct pci_dev *gpu_pdev,
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struct agp_bridge_data *bridge);
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void intel_gmch_remove(void);
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bool intel_enable_gtt(void);
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void intel_gtt_chipset_flush(void);
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void intel_gtt_insert_sg_entries(struct sg_table *st,
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unsigned int pg_start,
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unsigned int flags);
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void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries);
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/* Special gtt memory types */
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#define AGP_DCACHE_MEMORY 1
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#define AGP_PHYS_MEMORY 2
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/* New caching attributes for gen6/sandybridge */
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#define AGP_USER_CACHED_MEMORY_LLC_MLC (AGP_USER_TYPES + 2)
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#define AGP_USER_UNCACHED_MEMORY (AGP_USER_TYPES + 4)
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/* flag for GFDT type */
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#define AGP_USER_CACHED_MEMORY_GFDT (1 << 3)
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#ifdef CONFIG_INTEL_IOMMU
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extern int intel_iommu_gfx_mapped;
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#endif
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#endif
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