Vipul Pandya 42b6a94990 RDMA/cxgb4: Use DSGLs for fastreg and adapter memory writes for T5. ... It enables direct DMA by HW to memory region PBL arrays and fast register PBL arrays from host memory, vs the T4 way of passing these arrays in the WR itself. The result is lower latency for memory registration, and larger PBL array support for fast register operations. This patch also updates ULP_TX_MEM_WRITE command fields for T5. Ordering bit of ULP_TX_MEM_WRITE is at bit position 22 in T5 and at 23 in T4. Signed-off-by: Vipul Pandya <vipul@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>		2013-03-14 11:35:59 -04:00
..
cxgb4_main.c	RDMA/cxgb4: Turn off db coalescing when RDMA QPs are in use.	2013-03-14 11:35:58 -04:00
cxgb4_uld.h	RDMA/cxgb4: Turn off db coalescing when RDMA QPs are in use.	2013-03-14 11:35:58 -04:00
cxgb4.h	cxgb4: Disable SR-IOV support for PF4-7 for T5	2013-03-14 11:35:56 -04:00
l2t.c	cxgb4: Add T4 filter support	2012-12-19 09:28:19 -08:00
l2t.h	cxgb4: Add T4 filter support	2012-12-19 09:28:19 -08:00
Makefile
sge.c	cxgb4: Add T5 write combining support	2013-03-14 11:35:54 -04:00
t4_hw.c	cxgb4: Add T5 debugfs support	2013-03-14 11:35:55 -04:00
t4_hw.h	cxgb4: Initialize T5	2013-03-14 11:35:53 -04:00
t4_msg.h	RDMA/cxgb4: Use DSGLs for fastreg and adapter memory writes for T5.	2013-03-14 11:35:59 -04:00
t4_regs.h	RDMA/cxgb4: Turn off db coalescing when RDMA QPs are in use.	2013-03-14 11:35:58 -04:00
t4fw_api.h	cxgb4: Add macros, structures and inline functions for T5	2013-03-14 11:35:53 -04:00