Kuppuswamy Sathyanarayanan e6749c89b4 platform/x86: intel_pmc_ipc: fix gcr offset ... According to Broxton APL spec, PMC MIMO resources for Global Control Registers(GCR) are located at 4K(0x1000) offset from IPC base address. In this driver, PLAT_RESOURCE_GCR_OFFSET macro defines the offset of GCR region base address from IPC base address and its current value of 0x1008 is incorrect because it points to location for PMC_CFG register and not the GCR base address itself. GCR Base = IPC1 Base + 0x1000. This patch fixes this offset issue. Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>		2017-04-28 21:51:26 +03:00
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chrome	- Core Frameworks	2017-02-23 08:18:01 -08:00
goldfish	goldfish: Sanitize the broken interrupt handler	2017-02-15 08:49:58 -08:00
mips	Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus	2016-05-19 10:02:26 -07:00
olpc	platform/olpc: Make ec explicitly non-modular	2016-08-28 22:31:52 -07:00
x86	platform/x86: intel_pmc_ipc: fix gcr offset	2017-04-28 21:51:26 +03:00
Kconfig	goldfish: refactor goldfish platform configs	2016-01-28 23:34:36 -08:00
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