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e66796b9bb
Describe [H]SCIFs in the R8A7792 device tree. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
325 lines
9.7 KiB
Plaintext
325 lines
9.7 KiB
Plaintext
/*
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* Device Tree Source for the r8a7792 SoC
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*
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* Copyright (C) 2016 Cogent Embedded Inc.
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#include <dt-bindings/clock/r8a7792-clock.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/r8a7792-sysc.h>
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/ {
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compatible = "renesas,r8a7792";
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0>;
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clock-frequency = <1000000000>;
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clocks = <&cpg_clocks R8A7792_CLK_Z>;
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power-domains = <&sysc R8A7792_PD_CA15_CPU0>;
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next-level-cache = <&L2_CA15>;
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};
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L2_CA15: cache-controller@0 {
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compatible = "cache";
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reg = <0>;
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cache-unified;
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cache-level = <2>;
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power-domains = <&sysc R8A7792_PD_CA15_SCU>;
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};
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};
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soc {
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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gic: interrupt-controller@f1001000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0 0xf1001000 0 0x1000>,
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<0 0xf1002000 0 0x1000>,
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<0 0xf1004000 0 0x2000>,
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<0 0xf1006000 0 0x2000>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_LEVEL_HIGH)>;
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_LEVEL_LOW)>;
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};
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sysc: system-controller@e6180000 {
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compatible = "renesas,r8a7792-sysc";
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reg = <0 0xe6180000 0 0x0200>;
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#power-domain-cells = <1>;
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};
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dmac0: dma-controller@e6700000 {
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compatible = "renesas,dmac-r8a7792",
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"renesas,rcar-dmac";
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reg = <0 0xe6700000 0 0x20000>;
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interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "error",
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"ch0", "ch1", "ch2", "ch3",
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"ch4", "ch5", "ch6", "ch7",
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"ch8", "ch9", "ch10", "ch11",
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"ch12", "ch13", "ch14";
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clocks = <&mstp2_clks R8A7792_CLK_SYS_DMAC0>;
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clock-names = "fck";
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power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
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#dma-cells = <1>;
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dma-channels = <15>;
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};
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dmac1: dma-controller@e6720000 {
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compatible = "renesas,dmac-r8a7792",
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"renesas,rcar-dmac";
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reg = <0 0xe6720000 0 0x20000>;
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interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "error",
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"ch0", "ch1", "ch2", "ch3",
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"ch4", "ch5", "ch6", "ch7",
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"ch8", "ch9", "ch10", "ch11",
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"ch12", "ch13", "ch14";
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clocks = <&mstp2_clks R8A7792_CLK_SYS_DMAC1>;
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clock-names = "fck";
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power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
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#dma-cells = <1>;
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dma-channels = <15>;
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};
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scif0: serial@e6e60000 {
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compatible = "renesas,scif-r8a7792",
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"renesas,rcar-gen2-scif", "renesas,scif";
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reg = <0 0xe6e60000 0 64>;
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interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp7_clks R8A7792_CLK_SCIF0>, <&zs_clk>,
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<&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
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<&dmac1 0x29>, <&dmac1 0x2a>;
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dma-names = "tx", "rx", "tx", "rx";
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power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
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status = "disabled";
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};
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scif1: serial@e6e68000 {
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compatible = "renesas,scif-r8a7792",
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"renesas,rcar-gen2-scif", "renesas,scif";
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reg = <0 0xe6e68000 0 64>;
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interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp7_clks R8A7792_CLK_SCIF1>, <&zs_clk>,
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<&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
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<&dmac1 0x2d>, <&dmac1 0x2e>;
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dma-names = "tx", "rx", "tx", "rx";
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power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
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status = "disabled";
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};
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scif2: serial@e6e58000 {
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compatible = "renesas,scif-r8a7792",
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"renesas,rcar-gen2-scif", "renesas,scif";
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reg = <0 0xe6e58000 0 64>;
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interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp7_clks R8A7792_CLK_SCIF2>, <&zs_clk>,
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<&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
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<&dmac1 0x2b>, <&dmac1 0x2c>;
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dma-names = "tx", "rx", "tx", "rx";
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power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
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status = "disabled";
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};
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scif3: serial@e6ea8000 {
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compatible = "renesas,scif-r8a7792",
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"renesas,rcar-gen2-scif", "renesas,scif";
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reg = <0 0xe6ea8000 0 64>;
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interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp7_clks R8A7792_CLK_SCIF3>, <&zs_clk>,
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<&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
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<&dmac1 0x2f>, <&dmac1 0x30>;
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dma-names = "tx", "rx", "tx", "rx";
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power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
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status = "disabled";
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};
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hscif0: serial@e62c0000 {
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compatible = "renesas,hscif-r8a7792",
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"renesas,rcar-gen2-hscif", "renesas,hscif";
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reg = <0 0xe62c0000 0 96>;
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interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp7_clks R8A7792_CLK_HSCIF0>, <&zs_clk>,
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<&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
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<&dmac1 0x39>, <&dmac1 0x3a>;
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dma-names = "tx", "rx", "tx", "rx";
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power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
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status = "disabled";
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};
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hscif1: serial@e62c8000 {
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compatible = "renesas,hscif-r8a7792",
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"renesas,rcar-gen2-hscif", "renesas,hscif";
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reg = <0 0xe62c8000 0 96>;
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interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp7_clks R8A7792_CLK_HSCIF1>, <&zs_clk>,
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<&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
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<&dmac1 0x4d>, <&dmac1 0x4e>;
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dma-names = "tx", "rx", "tx", "rx";
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power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
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status = "disabled";
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};
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/* Special CPG clocks */
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cpg_clocks: cpg_clocks@e6150000 {
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compatible = "renesas,r8a7792-cpg-clocks",
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"renesas,rcar-gen2-cpg-clocks";
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reg = <0 0xe6150000 0 0x1000>;
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clocks = <&extal_clk>;
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#clock-cells = <1>;
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clock-output-names = "main", "pll0", "pll1", "pll3",
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"lb", "qspi", "z", "adsp";
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#power-domain-cells = <0>;
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};
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/* Fixed factor clocks */
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zs_clk: zs {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
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#clock-cells = <0>;
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clock-div = <6>;
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clock-mult = <1>;
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};
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p_clk: p {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
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#clock-cells = <0>;
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clock-div = <24>;
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clock-mult = <1>;
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};
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cp_clk: cp {
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
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#clock-cells = <0>;
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clock-div = <48>;
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clock-mult = <1>;
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};
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/* Gate clocks */
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mstp2_clks: mstp2_clks@e6150138 {
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compatible = "renesas,r8a7792-mstp-clocks",
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"renesas,cpg-mstp-clocks";
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reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
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clocks = <&zs_clk>, <&zs_clk>;
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#clock-cells = <1>;
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clock-indices = <
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R8A7792_CLK_SYS_DMAC1 R8A7792_CLK_SYS_DMAC0
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>;
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clock-output-names = "sys-dmac1", "sys-dmac0";
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};
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mstp4_clks: mstp4_clks@e6150140 {
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compatible = "renesas,r8a7792-mstp-clocks",
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"renesas,cpg-mstp-clocks";
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reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
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clocks = <&cp_clk>;
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#clock-cells = <1>;
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clock-indices = <R8A7792_CLK_IRQC>;
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clock-output-names = "irqc";
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};
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mstp7_clks: mstp7_clks@e615014c {
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compatible = "renesas,r8a7792-mstp-clocks",
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"renesas,cpg-mstp-clocks";
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reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
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clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>,
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<&p_clk>, <&p_clk>;
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#clock-cells = <1>;
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clock-indices = <
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R8A7792_CLK_HSCIF1 R8A7792_CLK_HSCIF0
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R8A7792_CLK_SCIF3 R8A7792_CLK_SCIF2
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R8A7792_CLK_SCIF1 R8A7792_CLK_SCIF0
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>;
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clock-output-names = "hscif1", "hscif0", "scif3",
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"scif2", "scif1", "scif0";
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};
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};
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/* External root clock */
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extal_clk: extal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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/* This value must be overridden by the board. */
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clock-frequency = <0>;
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};
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/* External SCIF clock */
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scif_clk: scif {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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/* This value must be overridden by the board. */
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clock-frequency = <0>;
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};
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};
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