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e2ad626f8f
It has been pointed out that naming a subsystem "genpd" isn't very self-explanatory and the acronym itself that means Generic PM Domain, is known only by a limited group of people. In a way to improve the situation, let's rename the subsystem to pmdomain, which ideally should indicate that this is about so called Power Domains or "PM domains" as we often also use within the Linux Kernel terminology. Suggested-by: Rafael J. Wysocki <rafael@kernel.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Rafael J. Wysocki <rafael@kernel.org> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230912221127.487327-1-ulf.hansson@linaro.org
364 lines
9.6 KiB
C
364 lines
9.6 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (c) 2013 Broadcom
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* Copyright (C) 2020 Rafał Miłecki <rafal@milecki.pl>
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*/
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#include <dt-bindings/soc/bcm-pmb.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pm_domain.h>
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#include <linux/reset/bcm63xx_pmb.h>
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#define BPCM_ID_REG 0x00
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#define BPCM_CAPABILITIES 0x04
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#define BPCM_CAP_NUM_ZONES 0x000000ff
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#define BPCM_CAP_SR_REG_BITS 0x0000ff00
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#define BPCM_CAP_PLLTYPE 0x00030000
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#define BPCM_CAP_UBUS 0x00080000
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#define BPCM_CONTROL 0x08
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#define BPCM_STATUS 0x0c
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#define BPCM_ROSC_CONTROL 0x10
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#define BPCM_ROSC_THRESH_H 0x14
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#define BPCM_ROSC_THRESHOLD_BCM6838 0x14
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#define BPCM_ROSC_THRESH_S 0x18
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#define BPCM_ROSC_COUNT_BCM6838 0x18
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#define BPCM_ROSC_COUNT 0x1c
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#define BPCM_PWD_CONTROL_BCM6838 0x1c
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#define BPCM_PWD_CONTROL 0x20
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#define BPCM_SR_CONTROL_BCM6838 0x20
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#define BPCM_PWD_ACCUM_CONTROL 0x24
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#define BPCM_SR_CONTROL 0x28
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#define BPCM_GLOBAL_CONTROL 0x2c
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#define BPCM_MISC_CONTROL 0x30
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#define BPCM_MISC_CONTROL2 0x34
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#define BPCM_SGPHY_CNTL 0x38
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#define BPCM_SGPHY_STATUS 0x3c
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#define BPCM_ZONE0 0x40
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#define BPCM_ZONE_CONTROL 0x00
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#define BPCM_ZONE_CONTROL_MANUAL_CLK_EN 0x00000001
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#define BPCM_ZONE_CONTROL_MANUAL_RESET_CTL 0x00000002
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#define BPCM_ZONE_CONTROL_FREQ_SCALE_USED 0x00000004 /* R/O */
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#define BPCM_ZONE_CONTROL_DPG_CAPABLE 0x00000008 /* R/O */
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#define BPCM_ZONE_CONTROL_MANUAL_MEM_PWR 0x00000030
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#define BPCM_ZONE_CONTROL_MANUAL_ISO_CTL 0x00000040
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#define BPCM_ZONE_CONTROL_MANUAL_CTL 0x00000080
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#define BPCM_ZONE_CONTROL_DPG_CTL_EN 0x00000100
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#define BPCM_ZONE_CONTROL_PWR_DN_REQ 0x00000200
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#define BPCM_ZONE_CONTROL_PWR_UP_REQ 0x00000400
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#define BPCM_ZONE_CONTROL_MEM_PWR_CTL_EN 0x00000800
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#define BPCM_ZONE_CONTROL_BLK_RESET_ASSERT 0x00001000
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#define BPCM_ZONE_CONTROL_MEM_STBY 0x00002000
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#define BPCM_ZONE_CONTROL_RESERVED 0x0007c000
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#define BPCM_ZONE_CONTROL_PWR_CNTL_STATE 0x00f80000
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#define BPCM_ZONE_CONTROL_FREQ_SCALAR_DYN_SEL 0x01000000 /* R/O */
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#define BPCM_ZONE_CONTROL_PWR_OFF_STATE 0x02000000 /* R/O */
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#define BPCM_ZONE_CONTROL_PWR_ON_STATE 0x04000000 /* R/O */
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#define BPCM_ZONE_CONTROL_PWR_GOOD 0x08000000 /* R/O */
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#define BPCM_ZONE_CONTROL_DPG_PWR_STATE 0x10000000 /* R/O */
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#define BPCM_ZONE_CONTROL_MEM_PWR_STATE 0x20000000 /* R/O */
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#define BPCM_ZONE_CONTROL_ISO_STATE 0x40000000 /* R/O */
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#define BPCM_ZONE_CONTROL_RESET_STATE 0x80000000 /* R/O */
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#define BPCM_ZONE_CONFIG1 0x04
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#define BPCM_ZONE_CONFIG2 0x08
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#define BPCM_ZONE_FREQ_SCALAR_CONTROL 0x0c
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#define BPCM_ZONE_SIZE 0x10
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struct bcm_pmb {
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struct device *dev;
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void __iomem *base;
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spinlock_t lock;
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bool little_endian;
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struct genpd_onecell_data genpd_onecell_data;
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};
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struct bcm_pmb_pd_data {
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const char * const name;
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int id;
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u8 bus;
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u8 device;
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};
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struct bcm_pmb_pm_domain {
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struct bcm_pmb *pmb;
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const struct bcm_pmb_pd_data *data;
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struct generic_pm_domain genpd;
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};
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static int bcm_pmb_bpcm_read(struct bcm_pmb *pmb, int bus, u8 device,
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int offset, u32 *val)
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{
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void __iomem *base = pmb->base + bus * 0x20;
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unsigned long flags;
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int err;
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spin_lock_irqsave(&pmb->lock, flags);
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err = bpcm_rd(base, device, offset, val);
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spin_unlock_irqrestore(&pmb->lock, flags);
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if (!err)
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*val = pmb->little_endian ? le32_to_cpu(*val) : be32_to_cpu(*val);
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return err;
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}
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static int bcm_pmb_bpcm_write(struct bcm_pmb *pmb, int bus, u8 device,
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int offset, u32 val)
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{
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void __iomem *base = pmb->base + bus * 0x20;
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unsigned long flags;
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int err;
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val = pmb->little_endian ? cpu_to_le32(val) : cpu_to_be32(val);
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spin_lock_irqsave(&pmb->lock, flags);
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err = bpcm_wr(base, device, offset, val);
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spin_unlock_irqrestore(&pmb->lock, flags);
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return err;
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}
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static int bcm_pmb_power_off_zone(struct bcm_pmb *pmb, int bus, u8 device,
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int zone)
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{
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int offset;
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u32 val;
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int err;
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offset = BPCM_ZONE0 + zone * BPCM_ZONE_SIZE + BPCM_ZONE_CONTROL;
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err = bcm_pmb_bpcm_read(pmb, bus, device, offset, &val);
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if (err)
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return err;
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val |= BPCM_ZONE_CONTROL_PWR_DN_REQ;
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val &= ~BPCM_ZONE_CONTROL_PWR_UP_REQ;
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err = bcm_pmb_bpcm_write(pmb, bus, device, offset, val);
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return err;
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}
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static int bcm_pmb_power_on_zone(struct bcm_pmb *pmb, int bus, u8 device,
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int zone)
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{
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int offset;
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u32 val;
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int err;
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offset = BPCM_ZONE0 + zone * BPCM_ZONE_SIZE + BPCM_ZONE_CONTROL;
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err = bcm_pmb_bpcm_read(pmb, bus, device, offset, &val);
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if (err)
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return err;
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if (!(val & BPCM_ZONE_CONTROL_PWR_ON_STATE)) {
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val &= ~BPCM_ZONE_CONTROL_PWR_DN_REQ;
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val |= BPCM_ZONE_CONTROL_DPG_CTL_EN;
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val |= BPCM_ZONE_CONTROL_PWR_UP_REQ;
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val |= BPCM_ZONE_CONTROL_MEM_PWR_CTL_EN;
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val |= BPCM_ZONE_CONTROL_BLK_RESET_ASSERT;
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err = bcm_pmb_bpcm_write(pmb, bus, device, offset, val);
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}
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return err;
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}
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static int bcm_pmb_power_off_device(struct bcm_pmb *pmb, int bus, u8 device)
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{
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int offset;
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u32 val;
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int err;
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/* Entire device can be powered off by powering off the 0th zone */
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offset = BPCM_ZONE0 + BPCM_ZONE_CONTROL;
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err = bcm_pmb_bpcm_read(pmb, bus, device, offset, &val);
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if (err)
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return err;
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if (!(val & BPCM_ZONE_CONTROL_PWR_OFF_STATE)) {
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val = BPCM_ZONE_CONTROL_PWR_DN_REQ;
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err = bcm_pmb_bpcm_write(pmb, bus, device, offset, val);
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}
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return err;
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}
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static int bcm_pmb_power_on_device(struct bcm_pmb *pmb, int bus, u8 device)
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{
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u32 val;
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int err;
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int i;
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err = bcm_pmb_bpcm_read(pmb, bus, device, BPCM_CAPABILITIES, &val);
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if (err)
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return err;
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for (i = 0; i < (val & BPCM_CAP_NUM_ZONES); i++) {
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err = bcm_pmb_power_on_zone(pmb, bus, device, i);
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if (err)
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return err;
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}
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return err;
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}
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static int bcm_pmb_power_on_sata(struct bcm_pmb *pmb, int bus, u8 device)
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{
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int err;
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err = bcm_pmb_power_on_zone(pmb, bus, device, 0);
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if (err)
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return err;
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/* Does not apply to the BCM963158 */
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err = bcm_pmb_bpcm_write(pmb, bus, device, BPCM_MISC_CONTROL, 0);
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if (err)
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return err;
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err = bcm_pmb_bpcm_write(pmb, bus, device, BPCM_SR_CONTROL, 0xffffffff);
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if (err)
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return err;
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err = bcm_pmb_bpcm_write(pmb, bus, device, BPCM_SR_CONTROL, 0);
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return err;
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}
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static int bcm_pmb_power_on(struct generic_pm_domain *genpd)
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{
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struct bcm_pmb_pm_domain *pd = container_of(genpd, struct bcm_pmb_pm_domain, genpd);
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const struct bcm_pmb_pd_data *data = pd->data;
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struct bcm_pmb *pmb = pd->pmb;
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switch (data->id) {
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case BCM_PMB_PCIE0:
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case BCM_PMB_PCIE1:
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case BCM_PMB_PCIE2:
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return bcm_pmb_power_on_zone(pmb, data->bus, data->device, 0);
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case BCM_PMB_HOST_USB:
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return bcm_pmb_power_on_device(pmb, data->bus, data->device);
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case BCM_PMB_SATA:
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return bcm_pmb_power_on_sata(pmb, data->bus, data->device);
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default:
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dev_err(pmb->dev, "unsupported device id: %d\n", data->id);
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return -EINVAL;
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}
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}
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static int bcm_pmb_power_off(struct generic_pm_domain *genpd)
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{
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struct bcm_pmb_pm_domain *pd = container_of(genpd, struct bcm_pmb_pm_domain, genpd);
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const struct bcm_pmb_pd_data *data = pd->data;
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struct bcm_pmb *pmb = pd->pmb;
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switch (data->id) {
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case BCM_PMB_PCIE0:
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case BCM_PMB_PCIE1:
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case BCM_PMB_PCIE2:
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return bcm_pmb_power_off_zone(pmb, data->bus, data->device, 0);
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case BCM_PMB_HOST_USB:
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return bcm_pmb_power_off_device(pmb, data->bus, data->device);
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default:
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dev_err(pmb->dev, "unsupported device id: %d\n", data->id);
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return -EINVAL;
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}
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}
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static int bcm_pmb_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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const struct bcm_pmb_pd_data *table;
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const struct bcm_pmb_pd_data *e;
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struct bcm_pmb *pmb;
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int max_id;
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int err;
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pmb = devm_kzalloc(dev, sizeof(*pmb), GFP_KERNEL);
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if (!pmb)
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return -ENOMEM;
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pmb->dev = dev;
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pmb->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(pmb->base))
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return PTR_ERR(pmb->base);
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spin_lock_init(&pmb->lock);
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pmb->little_endian = !of_device_is_big_endian(dev->of_node);
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table = of_device_get_match_data(dev);
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if (!table)
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return -EINVAL;
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max_id = 0;
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for (e = table; e->name; e++)
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max_id = max(max_id, e->id);
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pmb->genpd_onecell_data.num_domains = max_id + 1;
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pmb->genpd_onecell_data.domains =
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devm_kcalloc(dev, pmb->genpd_onecell_data.num_domains,
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sizeof(struct generic_pm_domain *), GFP_KERNEL);
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if (!pmb->genpd_onecell_data.domains)
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return -ENOMEM;
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for (e = table; e->name; e++) {
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struct bcm_pmb_pm_domain *pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
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if (!pd)
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return -ENOMEM;
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pd->pmb = pmb;
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pd->data = e;
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pd->genpd.name = e->name;
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pd->genpd.power_on = bcm_pmb_power_on;
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pd->genpd.power_off = bcm_pmb_power_off;
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pm_genpd_init(&pd->genpd, NULL, true);
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pmb->genpd_onecell_data.domains[e->id] = &pd->genpd;
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}
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err = of_genpd_add_provider_onecell(dev->of_node, &pmb->genpd_onecell_data);
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if (err) {
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dev_err(dev, "failed to add genpd provider: %d\n", err);
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return err;
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}
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return 0;
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}
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static const struct bcm_pmb_pd_data bcm_pmb_bcm4908_data[] = {
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{ .name = "pcie2", .id = BCM_PMB_PCIE2, .bus = 0, .device = 2, },
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{ .name = "pcie0", .id = BCM_PMB_PCIE0, .bus = 1, .device = 14, },
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{ .name = "pcie1", .id = BCM_PMB_PCIE1, .bus = 1, .device = 15, },
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{ .name = "usb", .id = BCM_PMB_HOST_USB, .bus = 1, .device = 17, },
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{ },
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};
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static const struct bcm_pmb_pd_data bcm_pmb_bcm63138_data[] = {
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{ .name = "sata", .id = BCM_PMB_SATA, .bus = 0, .device = 3, },
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{ },
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};
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static const struct of_device_id bcm_pmb_of_match[] = {
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{ .compatible = "brcm,bcm4908-pmb", .data = &bcm_pmb_bcm4908_data, },
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{ .compatible = "brcm,bcm63138-pmb", .data = &bcm_pmb_bcm63138_data, },
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{ },
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};
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static struct platform_driver bcm_pmb_driver = {
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.driver = {
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.name = "bcm-pmb",
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.of_match_table = bcm_pmb_of_match,
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},
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.probe = bcm_pmb_probe,
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};
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builtin_platform_driver(bcm_pmb_driver);
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