mirror of
https://github.com/torvalds/linux.git
synced 2024-12-03 17:41:22 +00:00
ccf5355d05
Since CONFIG_X86_64 selects CONFIG_X86_LOCAL_APIC, the following condition: #if defined(CONFIG_X86_64) || defined(CONFIG_X86_LOCAL_APIC) is equivalent to: #if defined(CONFIG_X86_LOCAL_APIC) ... and we can eliminate that #ifdef by providing an empty init_bsp_APIC() stub in the !CONFIG_X86_LOCAL_APIC case. Also add some comments to explain why we call init_bsp_APIC(). Signed-off-by: Dou Liyang <douly.fnst@cn.fujitsu.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: mroos@linux.ee Cc: ville.syrjala@linux.intel.com Link: http://lkml.kernel.org/r/20180117073748.23905-1-douly.fnst@cn.fujitsu.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
109 lines
2.7 KiB
C
109 lines
2.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
|
|
#include <linux/linkage.h>
|
|
#include <linux/errno.h>
|
|
#include <linux/signal.h>
|
|
#include <linux/sched.h>
|
|
#include <linux/ioport.h>
|
|
#include <linux/interrupt.h>
|
|
#include <linux/timex.h>
|
|
#include <linux/random.h>
|
|
#include <linux/kprobes.h>
|
|
#include <linux/init.h>
|
|
#include <linux/kernel_stat.h>
|
|
#include <linux/device.h>
|
|
#include <linux/bitops.h>
|
|
#include <linux/acpi.h>
|
|
#include <linux/io.h>
|
|
#include <linux/delay.h>
|
|
|
|
#include <linux/atomic.h>
|
|
#include <asm/timer.h>
|
|
#include <asm/hw_irq.h>
|
|
#include <asm/pgtable.h>
|
|
#include <asm/desc.h>
|
|
#include <asm/apic.h>
|
|
#include <asm/setup.h>
|
|
#include <asm/i8259.h>
|
|
#include <asm/traps.h>
|
|
#include <asm/prom.h>
|
|
|
|
/*
|
|
* ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts:
|
|
* (these are usually mapped to vectors 0x30-0x3f)
|
|
*/
|
|
|
|
/*
|
|
* The IO-APIC gives us many more interrupt sources. Most of these
|
|
* are unused but an SMP system is supposed to have enough memory ...
|
|
* sometimes (mostly wrt. hw bugs) we get corrupted vectors all
|
|
* across the spectrum, so we really want to be prepared to get all
|
|
* of these. Plus, more powerful systems might have more than 64
|
|
* IO-APIC registers.
|
|
*
|
|
* (these are usually mapped into the 0x30-0xff vector range)
|
|
*/
|
|
|
|
/*
|
|
* IRQ2 is cascade interrupt to second interrupt controller
|
|
*/
|
|
static struct irqaction irq2 = {
|
|
.handler = no_action,
|
|
.name = "cascade",
|
|
.flags = IRQF_NO_THREAD,
|
|
};
|
|
|
|
DEFINE_PER_CPU(vector_irq_t, vector_irq) = {
|
|
[0 ... NR_VECTORS - 1] = VECTOR_UNUSED,
|
|
};
|
|
|
|
void __init init_ISA_irqs(void)
|
|
{
|
|
struct irq_chip *chip = legacy_pic->chip;
|
|
int i;
|
|
|
|
/*
|
|
* Try to set up the through-local-APIC virtual wire mode earlier.
|
|
*
|
|
* On some 32-bit UP machines, whose APIC has been disabled by BIOS
|
|
* and then got re-enabled by "lapic", it hangs at boot time without this.
|
|
*/
|
|
init_bsp_APIC();
|
|
|
|
legacy_pic->init(0);
|
|
|
|
for (i = 0; i < nr_legacy_irqs(); i++)
|
|
irq_set_chip_and_handler(i, chip, handle_level_irq);
|
|
}
|
|
|
|
void __init init_IRQ(void)
|
|
{
|
|
int i;
|
|
|
|
/*
|
|
* On cpu 0, Assign ISA_IRQ_VECTOR(irq) to IRQ 0..15.
|
|
* If these IRQ's are handled by legacy interrupt-controllers like PIC,
|
|
* then this configuration will likely be static after the boot. If
|
|
* these IRQ's are handled by more mordern controllers like IO-APIC,
|
|
* then this vector space can be freed and re-used dynamically as the
|
|
* irq's migrate etc.
|
|
*/
|
|
for (i = 0; i < nr_legacy_irqs(); i++)
|
|
per_cpu(vector_irq, 0)[ISA_IRQ_VECTOR(i)] = irq_to_desc(i);
|
|
|
|
x86_init.irqs.intr_init();
|
|
}
|
|
|
|
void __init native_init_IRQ(void)
|
|
{
|
|
/* Execute any quirks before the call gates are initialised: */
|
|
x86_init.irqs.pre_vector_init();
|
|
|
|
idt_setup_apic_and_irq_gates();
|
|
lapic_assign_system_vectors();
|
|
|
|
if (!acpi_ioapic && !of_ioapic && nr_legacy_irqs())
|
|
setup_irq(2, &irq2);
|
|
|
|
irq_ctx_init(smp_processor_id());
|
|
}
|