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This patch adds SPR number for TAR, PPR, DSCR special purpose registers. It also adds TM, VSX, VMX related instructions which will then be used by patches later in the series. Now that the new DSCR register definitions (SPRN_DSCR_PRIV and SPRN_DSCR) are defined outside this directory, use them instead. Signed-off-by: Anshuman Khandual <khandual@linux.vnet.ibm.com> Signed-off-by: Simon Guo <wei.guo.simon@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
126 lines
2.6 KiB
C
126 lines
2.6 KiB
C
/*
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* POWER Data Stream Control Register (DSCR)
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*
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* This header file contains helper functions and macros
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* required for all the DSCR related test cases.
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*
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* Copyright 2012, Anton Blanchard, IBM Corporation.
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* Copyright 2015, Anshuman Khandual, IBM Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#ifndef _SELFTESTS_POWERPC_DSCR_DSCR_H
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#define _SELFTESTS_POWERPC_DSCR_DSCR_H
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#include <unistd.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <fcntl.h>
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#include <dirent.h>
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#include <pthread.h>
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#include <sched.h>
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#include <sys/types.h>
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#include <sys/stat.h>
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#include <sys/wait.h>
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#include "utils.h"
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#define THREADS 100 /* Max threads */
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#define COUNT 100 /* Max iterations */
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#define DSCR_MAX 16 /* Max DSCR value */
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#define LEN_MAX 100 /* Max name length */
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#define DSCR_DEFAULT "/sys/devices/system/cpu/dscr_default"
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#define CPU_PATH "/sys/devices/system/cpu/"
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#define rmb() asm volatile("lwsync":::"memory")
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#define wmb() asm volatile("lwsync":::"memory")
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#define ACCESS_ONCE(x) (*(volatile typeof(x) *)&(x))
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/* Prilvilege state DSCR access */
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inline unsigned long get_dscr(void)
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{
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unsigned long ret;
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asm volatile("mfspr %0,%1" : "=r" (ret) : "i" (SPRN_DSCR_PRIV));
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return ret;
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}
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inline void set_dscr(unsigned long val)
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{
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asm volatile("mtspr %1,%0" : : "r" (val), "i" (SPRN_DSCR_PRIV));
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}
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/* Problem state DSCR access */
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inline unsigned long get_dscr_usr(void)
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{
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unsigned long ret;
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asm volatile("mfspr %0,%1" : "=r" (ret) : "i" (SPRN_DSCR));
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return ret;
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}
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inline void set_dscr_usr(unsigned long val)
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{
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asm volatile("mtspr %1,%0" : : "r" (val), "i" (SPRN_DSCR));
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}
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/* Default DSCR access */
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unsigned long get_default_dscr(void)
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{
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int fd = -1, ret;
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char buf[16];
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unsigned long val;
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if (fd == -1) {
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fd = open(DSCR_DEFAULT, O_RDONLY);
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if (fd == -1) {
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perror("open() failed");
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exit(1);
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}
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}
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memset(buf, 0, sizeof(buf));
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lseek(fd, 0, SEEK_SET);
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ret = read(fd, buf, sizeof(buf));
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if (ret == -1) {
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perror("read() failed");
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exit(1);
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}
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sscanf(buf, "%lx", &val);
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close(fd);
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return val;
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}
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void set_default_dscr(unsigned long val)
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{
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int fd = -1, ret;
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char buf[16];
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if (fd == -1) {
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fd = open(DSCR_DEFAULT, O_RDWR);
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if (fd == -1) {
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perror("open() failed");
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exit(1);
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}
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}
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sprintf(buf, "%lx\n", val);
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ret = write(fd, buf, strlen(buf));
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if (ret == -1) {
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perror("write() failed");
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exit(1);
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}
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close(fd);
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}
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double uniform_deviate(int seed)
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{
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return seed * (1.0 / (RAND_MAX + 1.0));
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}
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#endif /* _SELFTESTS_POWERPC_DSCR_DSCR_H */
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