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Architecturally, TLBs are private to the (physical) CPU they're associated with. But when multiple vcpus from the same VM are being multiplexed on the same CPU, the TLBs are not private to the vcpus (and are actually shared across the VMID). Let's consider the following scenario: - vcpu-0 maps PA to VA - vcpu-1 maps PA' to VA If run on the same physical CPU, vcpu-1 can hit TLB entries generated by vcpu-0 accesses, and access the wrong physical page. The solution to this is to keep a per-VM map of which vcpu ran last on each given physical CPU, and invalidate local TLBs when switching to a different vcpu from the same VM. Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
89 lines
2.1 KiB
C
89 lines
2.1 KiB
C
/*
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* Copyright (C) 2015 - ARM Ltd
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <asm/kvm_hyp.h>
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void __hyp_text __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa)
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{
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dsb(ishst);
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/* Switch to requested VMID */
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kvm = kern_hyp_va(kvm);
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write_sysreg(kvm->arch.vttbr, vttbr_el2);
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isb();
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/*
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* We could do so much better if we had the VA as well.
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* Instead, we invalidate Stage-2 for this IPA, and the
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* whole of Stage-1. Weep...
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*/
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ipa >>= 12;
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asm volatile("tlbi ipas2e1is, %0" : : "r" (ipa));
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/*
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* We have to ensure completion of the invalidation at Stage-2,
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* since a table walk on another CPU could refill a TLB with a
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* complete (S1 + S2) walk based on the old Stage-2 mapping if
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* the Stage-1 invalidation happened first.
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*/
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dsb(ish);
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asm volatile("tlbi vmalle1is" : : );
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dsb(ish);
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isb();
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write_sysreg(0, vttbr_el2);
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}
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void __hyp_text __kvm_tlb_flush_vmid(struct kvm *kvm)
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{
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dsb(ishst);
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/* Switch to requested VMID */
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kvm = kern_hyp_va(kvm);
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write_sysreg(kvm->arch.vttbr, vttbr_el2);
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isb();
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asm volatile("tlbi vmalls12e1is" : : );
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dsb(ish);
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isb();
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write_sysreg(0, vttbr_el2);
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}
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void __hyp_text __kvm_tlb_flush_local_vmid(struct kvm_vcpu *vcpu)
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{
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struct kvm *kvm = kern_hyp_va(kern_hyp_va(vcpu)->kvm);
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/* Switch to requested VMID */
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write_sysreg(kvm->arch.vttbr, vttbr_el2);
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isb();
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asm volatile("tlbi vmalle1" : : );
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dsb(nsh);
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isb();
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write_sysreg(0, vttbr_el2);
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}
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void __hyp_text __kvm_flush_vm_context(void)
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{
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dsb(ishst);
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asm volatile("tlbi alle1is \n"
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"ic ialluis ": : );
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dsb(ish);
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}
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