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4d22de3e6c
This driver is required by the Chelsio T3 RDMA driver posted by Steve Wise. Signed-off-by: Divy Le Ray <divy@chelsio.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
145 lines
5.0 KiB
C
145 lines
5.0 KiB
C
/*
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* ----------------------------------------------------------------------------
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* >>>>>>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<<
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* ----------------------------------------------------------------------------
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* Copyright 2004 (C) Chelsio Communications, Inc. (Chelsio)
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*
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* Chelsio Communications, Inc. owns the sole copyright to this software.
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* You may not make a copy, you may not derive works herefrom, and you may
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* not distribute this work to others. Other restrictions of rights may apply
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* as well. This is unpublished, confidential information. All rights reserved.
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* This software contains confidential information and trade secrets of Chelsio
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* Communications, Inc. Use, disclosure, or reproduction is prohibited without
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* the prior express written permission of Chelsio Communications, Inc.
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* ----------------------------------------------------------------------------
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* >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> Warranty <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
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* ----------------------------------------------------------------------------
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* CHELSIO MAKES NO WARRANTY OF ANY KIND WITH REGARD TO THE USE OF THIS
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* SOFTWARE, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
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* ----------------------------------------------------------------------------
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*
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* This is the firmware_exports.h header file, firmware interface defines.
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*
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* Written January 2005 by felix marti (felix@chelsio.com)
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*/
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#ifndef _FIRMWARE_EXPORTS_H_
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#define _FIRMWARE_EXPORTS_H_
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/* WR OPCODES supported by the firmware.
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*/
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#define FW_WROPCODE_FORWARD 0x01
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#define FW_WROPCODE_BYPASS 0x05
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#define FW_WROPCODE_TUNNEL_TX_PKT 0x03
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#define FW_WROPOCDE_ULPTX_DATA_SGL 0x00
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#define FW_WROPCODE_ULPTX_MEM_READ 0x02
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#define FW_WROPCODE_ULPTX_PKT 0x04
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#define FW_WROPCODE_ULPTX_INVALIDATE 0x06
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#define FW_WROPCODE_TUNNEL_RX_PKT 0x07
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#define FW_WROPCODE_OFLD_GETTCB_RPL 0x08
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#define FW_WROPCODE_OFLD_CLOSE_CON 0x09
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#define FW_WROPCODE_OFLD_TP_ABORT_CON_REQ 0x0A
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#define FW_WROPCODE_OFLD_HOST_ABORT_CON_RPL 0x0F
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#define FW_WROPCODE_OFLD_HOST_ABORT_CON_REQ 0x0B
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#define FW_WROPCODE_OFLD_TP_ABORT_CON_RPL 0x0C
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#define FW_WROPCODE_OFLD_TX_DATA 0x0D
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#define FW_WROPCODE_OFLD_TX_DATA_ACK 0x0E
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#define FW_WROPCODE_RI_RDMA_INIT 0x10
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#define FW_WROPCODE_RI_RDMA_WRITE 0x11
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#define FW_WROPCODE_RI_RDMA_READ_REQ 0x12
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#define FW_WROPCODE_RI_RDMA_READ_RESP 0x13
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#define FW_WROPCODE_RI_SEND 0x14
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#define FW_WROPCODE_RI_TERMINATE 0x15
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#define FW_WROPCODE_RI_RDMA_READ 0x16
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#define FW_WROPCODE_RI_RECEIVE 0x17
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#define FW_WROPCODE_RI_BIND_MW 0x18
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#define FW_WROPCODE_RI_FASTREGISTER_MR 0x19
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#define FW_WROPCODE_RI_LOCAL_INV 0x1A
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#define FW_WROPCODE_RI_MODIFY_QP 0x1B
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#define FW_WROPCODE_RI_BYPASS 0x1C
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#define FW_WROPOCDE_RSVD 0x1E
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#define FW_WROPCODE_SGE_EGRESSCONTEXT_RR 0x1F
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#define FW_WROPCODE_MNGT 0x1D
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#define FW_MNGTOPCODE_PKTSCHED_SET 0x00
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/* Maximum size of a WR sent from the host, limited by the SGE.
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*
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* Note: WR coming from ULP or TP are only limited by CIM.
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*/
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#define FW_WR_SIZE 128
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/* Maximum number of outstanding WRs sent from the host. Value must be
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* programmed in the CTRL/TUNNEL/QP SGE Egress Context and used by
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* offload modules to limit the number of WRs per connection.
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*/
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#define FW_T3_WR_NUM 16
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#define FW_N3_WR_NUM 7
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#ifndef N3
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# define FW_WR_NUM FW_T3_WR_NUM
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#else
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# define FW_WR_NUM FW_N3_WR_NUM
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#endif
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/* FW_TUNNEL_NUM corresponds to the number of supported TUNNEL Queues. These
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* queues must start at SGE Egress Context FW_TUNNEL_SGEEC_START and must
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* start at 'TID' (or 'uP Token') FW_TUNNEL_TID_START.
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*
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* Ingress Traffic (e.g. DMA completion credit) for TUNNEL Queue[i] is sent
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* to RESP Queue[i].
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*/
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#define FW_TUNNEL_NUM 8
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#define FW_TUNNEL_SGEEC_START 8
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#define FW_TUNNEL_TID_START 65544
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/* FW_CTRL_NUM corresponds to the number of supported CTRL Queues. These queues
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* must start at SGE Egress Context FW_CTRL_SGEEC_START and must start at 'TID'
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* (or 'uP Token') FW_CTRL_TID_START.
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*
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* Ingress Traffic for CTRL Queue[i] is sent to RESP Queue[i].
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*/
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#define FW_CTRL_NUM 8
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#define FW_CTRL_SGEEC_START 65528
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#define FW_CTRL_TID_START 65536
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/* FW_OFLD_NUM corresponds to the number of supported OFFLOAD Queues. These
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* queues must start at SGE Egress Context FW_OFLD_SGEEC_START.
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*
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* Note: the 'uP Token' in the SGE Egress Context fields is irrelevant for
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* OFFLOAD Queues, as the host is responsible for providing the correct TID in
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* every WR.
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*
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* Ingress Trafffic for OFFLOAD Queue[i] is sent to RESP Queue[i].
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*/
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#define FW_OFLD_NUM 8
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#define FW_OFLD_SGEEC_START 0
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/*
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*
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*/
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#define FW_RI_NUM 1
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#define FW_RI_SGEEC_START 65527
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#define FW_RI_TID_START 65552
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/*
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* The RX_PKT_TID
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*/
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#define FW_RX_PKT_NUM 1
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#define FW_RX_PKT_TID_START 65553
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/* FW_WRC_NUM corresponds to the number of Work Request Context that supported
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* by the firmware.
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*/
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#define FW_WRC_NUM \
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(65536 + FW_TUNNEL_NUM + FW_CTRL_NUM + FW_RI_NUM + FW_RX_PKT_NUM)
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#endif /* _FIRMWARE_EXPORTS_H_ */
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