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65c9ad77cb
Add a MODULE_DEVICE_TABLE() on all clocks that can be built as modules to allow auto-load at boot. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Tested-by: Miles Chen <miles.chen@mediatek.com> Tested-by: Chen-Yu Tsai <wenst@chromium.org> # MT8183, MT8192, MT8195 Chromebooks Link: https://lore.kernel.org/r/20230306140543.1813621-50-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
129 lines
3.5 KiB
C
129 lines
3.5 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2017 MediaTek Inc.
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* Copyright (c) 2023 Collabora, Ltd.
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* AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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*/
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#include <dt-bindings/clock/mt7622-clk.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include "clk-cpumux.h"
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#include "clk-gate.h"
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#include "clk-mtk.h"
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#include "reset.h"
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#define GATE_INFRA(_id, _name, _parent, _shift) \
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GATE_MTK(_id, _name, _parent, &infra_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
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static const struct mtk_gate_regs infra_cg_regs = {
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.set_ofs = 0x40,
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.clr_ofs = 0x44,
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.sta_ofs = 0x48,
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};
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static const char * const infra_mux1_parents[] = {
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"clkxtal",
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"armpll",
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"main_core_en",
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"armpll"
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};
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static const struct mtk_composite cpu_muxes[] = {
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MUX(CLK_INFRA_MUX1_SEL, "infra_mux1_sel", infra_mux1_parents, 0x000, 2, 2),
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};
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static const struct mtk_gate infra_clks[] = {
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GATE_INFRA(CLK_INFRA_DBGCLK_PD, "infra_dbgclk_pd", "axi_sel", 0),
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GATE_INFRA(CLK_INFRA_TRNG, "trng_ck", "axi_sel", 2),
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GATE_INFRA(CLK_INFRA_AUDIO_PD, "infra_audio_pd", "aud_intbus_sel", 5),
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GATE_INFRA(CLK_INFRA_IRRX_PD, "infra_irrx_pd", "irrx_sel", 16),
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GATE_INFRA(CLK_INFRA_APXGPT_PD, "infra_apxgpt_pd", "f10m_ref_sel", 18),
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GATE_INFRA(CLK_INFRA_PMIC_PD, "infra_pmic_pd", "pmicspi_sel", 22),
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};
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static u16 infrasys_rst_ofs[] = { 0x30 };
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static const struct mtk_clk_rst_desc clk_rst_desc = {
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.version = MTK_RST_SIMPLE,
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.rst_bank_ofs = infrasys_rst_ofs,
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.rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs),
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};
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static const struct of_device_id of_match_clk_mt7622_infracfg[] = {
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{ .compatible = "mediatek,mt7622-infracfg" },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, of_match_clk_mt7622_infracfg);
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static int clk_mt7622_infracfg_probe(struct platform_device *pdev)
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{
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struct clk_hw_onecell_data *clk_data;
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struct device_node *node = pdev->dev.of_node;
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void __iomem *base;
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int ret;
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base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(base))
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return PTR_ERR(base);
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clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
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if (!clk_data)
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return -ENOMEM;
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ret = mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
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if (ret)
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goto free_clk_data;
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ret = mtk_clk_register_gates(&pdev->dev, node, infra_clks,
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ARRAY_SIZE(infra_clks), clk_data);
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if (ret)
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goto free_clk_data;
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ret = mtk_clk_register_cpumuxes(&pdev->dev, node, cpu_muxes,
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ARRAY_SIZE(cpu_muxes), clk_data);
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if (ret)
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goto unregister_gates;
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ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
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if (ret)
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goto unregister_cpumuxes;
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return 0;
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unregister_cpumuxes:
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mtk_clk_unregister_cpumuxes(cpu_muxes, ARRAY_SIZE(cpu_muxes), clk_data);
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unregister_gates:
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mtk_clk_unregister_gates(infra_clks, ARRAY_SIZE(infra_clks), clk_data);
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free_clk_data:
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mtk_free_clk_data(clk_data);
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return ret;
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}
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static int clk_mt7622_infracfg_remove(struct platform_device *pdev)
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{
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struct device_node *node = pdev->dev.of_node;
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struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
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of_clk_del_provider(node);
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mtk_clk_unregister_cpumuxes(cpu_muxes, ARRAY_SIZE(cpu_muxes), clk_data);
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mtk_clk_unregister_gates(infra_clks, ARRAY_SIZE(infra_clks), clk_data);
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mtk_free_clk_data(clk_data);
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return 0;
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}
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static struct platform_driver clk_mt7622_infracfg_drv = {
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.driver = {
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.name = "clk-mt7622-infracfg",
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.of_match_table = of_match_clk_mt7622_infracfg,
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},
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.probe = clk_mt7622_infracfg_probe,
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.remove = clk_mt7622_infracfg_remove,
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};
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module_platform_driver(clk_mt7622_infracfg_drv);
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MODULE_DESCRIPTION("MediaTek MT7622 infracfg clocks driver");
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MODULE_LICENSE("GPL");
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