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When users set flow control using ethtool the bits are set properly in the CPGMAC_SL MACCONTROL register, but the FIFO depth in the respective Port n Maximum FIFO Blocks (Pn_MAX_BLKS) registers remains set to the minimum size reset value. When receive flow control is enabled on a port, the port's associated FIFO block allocation must be adjusted. The port RX allocation must increase to accommodate the flow control runout. The TRM recommends numbers of 5 or 6. Hence, apply required Port FIFO configuration to Pn_MAX_BLKS.Pn_TX_MAX_BLKS=0xF and Pn_MAX_BLKS.Pn_RX_MAX_BLKS=0x5 during interface initialization. Cc: Schuyler Patton <spatton@ti.com> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: David S. Miller <davem@davemloft.net> |
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| .. | ||
| cpmac.c | ||
| cpsw_ale.c | ||
| cpsw_ale.h | ||
| cpsw-common.c | ||
| cpsw-phy-sel.c | ||
| cpsw.c | ||
| cpsw.h | ||
| cpts.c | ||
| cpts.h | ||
| davinci_cpdma.c | ||
| davinci_cpdma.h | ||
| davinci_emac.c | ||
| davinci_mdio.c | ||
| Kconfig | ||
| Makefile | ||
| netcp_core.c | ||
| netcp_ethss.c | ||
| netcp_sgmii.c | ||
| netcp_xgbepcsr.c | ||
| netcp.h | ||
| tlan.c | ||
| tlan.h | ||