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The commit a2be01b (ARM: only include mach/irqs.h for !SPARSE_IRQ)
makes mach/irqs.h only be included for !SPARSE_IRQ build. There are
a nubmer of platforms have FIQ_START defined in mach/irqs.h for FIQ
support.
arch/arm/mach-rpc/include/mach/irqs.h:#define FIQ_START 64
arch/arm/mach-s3c24xx/include/mach/irqs.h:#define FIQ_START IRQ_EINT0
arch/arm/plat-mxc/include/mach/irqs.h:#define FIQ_START 0
If SPARSE_IRQ is enabled for any of these platforms, the following
compile error will be seen.
arch/arm/kernel/fiq.c: In function ‘enable_fiq’:
arch/arm/kernel/fiq.c:127:19: error: ‘FIQ_START’ undeclared (first use in this function)
arch/arm/kernel/fiq.c:127:19: note: each undeclared identifier is reported only once for each function it appears in
arch/arm/kernel/fiq.c: In function ‘disable_fiq’:
arch/arm/kernel/fiq.c:132:20: error: ‘FIQ_START’ undeclared (first use in this function)
The patch changes fiq code to have init_FIQ take FIQ_START from
platforms as a parameter and assign it to variable fiq_start which
is to replace FIQ_START uses in enable_fiq/disable_fiq.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Rob Herring <rob.herring@calxeda.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
169 lines
3.4 KiB
C
169 lines
3.4 KiB
C
#include <linux/init.h>
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#include <linux/list.h>
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#include <linux/io.h>
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#include <asm/mach/irq.h>
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#include <asm/hardware/iomd.h>
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#include <asm/irq.h>
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#include <asm/fiq.h>
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static void iomd_ack_irq_a(struct irq_data *d)
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{
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unsigned int val, mask;
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mask = 1 << d->irq;
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val = iomd_readb(IOMD_IRQMASKA);
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iomd_writeb(val & ~mask, IOMD_IRQMASKA);
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iomd_writeb(mask, IOMD_IRQCLRA);
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}
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static void iomd_mask_irq_a(struct irq_data *d)
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{
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unsigned int val, mask;
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mask = 1 << d->irq;
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val = iomd_readb(IOMD_IRQMASKA);
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iomd_writeb(val & ~mask, IOMD_IRQMASKA);
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}
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static void iomd_unmask_irq_a(struct irq_data *d)
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{
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unsigned int val, mask;
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mask = 1 << d->irq;
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val = iomd_readb(IOMD_IRQMASKA);
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iomd_writeb(val | mask, IOMD_IRQMASKA);
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}
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static struct irq_chip iomd_a_chip = {
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.irq_ack = iomd_ack_irq_a,
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.irq_mask = iomd_mask_irq_a,
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.irq_unmask = iomd_unmask_irq_a,
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};
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static void iomd_mask_irq_b(struct irq_data *d)
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{
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unsigned int val, mask;
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mask = 1 << (d->irq & 7);
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val = iomd_readb(IOMD_IRQMASKB);
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iomd_writeb(val & ~mask, IOMD_IRQMASKB);
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}
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static void iomd_unmask_irq_b(struct irq_data *d)
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{
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unsigned int val, mask;
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mask = 1 << (d->irq & 7);
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val = iomd_readb(IOMD_IRQMASKB);
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iomd_writeb(val | mask, IOMD_IRQMASKB);
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}
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static struct irq_chip iomd_b_chip = {
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.irq_ack = iomd_mask_irq_b,
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.irq_mask = iomd_mask_irq_b,
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.irq_unmask = iomd_unmask_irq_b,
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};
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static void iomd_mask_irq_dma(struct irq_data *d)
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{
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unsigned int val, mask;
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mask = 1 << (d->irq & 7);
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val = iomd_readb(IOMD_DMAMASK);
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iomd_writeb(val & ~mask, IOMD_DMAMASK);
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}
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static void iomd_unmask_irq_dma(struct irq_data *d)
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{
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unsigned int val, mask;
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mask = 1 << (d->irq & 7);
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val = iomd_readb(IOMD_DMAMASK);
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iomd_writeb(val | mask, IOMD_DMAMASK);
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}
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static struct irq_chip iomd_dma_chip = {
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.irq_ack = iomd_mask_irq_dma,
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.irq_mask = iomd_mask_irq_dma,
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.irq_unmask = iomd_unmask_irq_dma,
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};
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static void iomd_mask_irq_fiq(struct irq_data *d)
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{
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unsigned int val, mask;
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mask = 1 << (d->irq & 7);
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val = iomd_readb(IOMD_FIQMASK);
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iomd_writeb(val & ~mask, IOMD_FIQMASK);
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}
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static void iomd_unmask_irq_fiq(struct irq_data *d)
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{
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unsigned int val, mask;
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mask = 1 << (d->irq & 7);
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val = iomd_readb(IOMD_FIQMASK);
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iomd_writeb(val | mask, IOMD_FIQMASK);
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}
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static struct irq_chip iomd_fiq_chip = {
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.irq_ack = iomd_mask_irq_fiq,
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.irq_mask = iomd_mask_irq_fiq,
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.irq_unmask = iomd_unmask_irq_fiq,
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};
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extern unsigned char rpc_default_fiq_start, rpc_default_fiq_end;
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void __init rpc_init_irq(void)
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{
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unsigned int irq, flags;
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iomd_writeb(0, IOMD_IRQMASKA);
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iomd_writeb(0, IOMD_IRQMASKB);
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iomd_writeb(0, IOMD_FIQMASK);
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iomd_writeb(0, IOMD_DMAMASK);
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set_fiq_handler(&rpc_default_fiq_start,
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&rpc_default_fiq_end - &rpc_default_fiq_start);
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for (irq = 0; irq < NR_IRQS; irq++) {
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flags = IRQF_VALID;
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if (irq <= 6 || (irq >= 9 && irq <= 15))
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flags |= IRQF_PROBE;
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if (irq == 21 || (irq >= 16 && irq <= 19) ||
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irq == IRQ_KEYBOARDTX)
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flags |= IRQF_NOAUTOEN;
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switch (irq) {
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case 0 ... 7:
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irq_set_chip_and_handler(irq, &iomd_a_chip,
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handle_level_irq);
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set_irq_flags(irq, flags);
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break;
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case 8 ... 15:
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irq_set_chip_and_handler(irq, &iomd_b_chip,
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handle_level_irq);
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set_irq_flags(irq, flags);
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break;
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case 16 ... 21:
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irq_set_chip_and_handler(irq, &iomd_dma_chip,
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handle_level_irq);
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set_irq_flags(irq, flags);
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break;
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case 64 ... 71:
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irq_set_chip(irq, &iomd_fiq_chip);
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set_irq_flags(irq, IRQF_VALID);
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break;
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}
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}
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init_FIQ(FIQ_START);
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}
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