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e68f31f452
This adds support for the Marvell Tauros3 cache controller which is compatible with pl310 cache controller but broadcasts L1 cache operations to L2 cache. While updating the binding documentation, clean up the list of possible compatibles. Also reorder driver compatibles to allow non-ARM derivated to be compatible to ARM cache controller compatibles. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> |
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| .. | ||
| arm_timer.h | ||
| cache-l2x0.h | ||
| cache-tauros2.h | ||
| coresight.h | ||
| dec21285.h | ||
| entry-macro-iomd.S | ||
| icst.h | ||
| ioc.h | ||
| iomd.h | ||
| iop3xx-adma.h | ||
| iop3xx.h | ||
| iop_adma.h | ||
| it8152.h | ||
| locomo.h | ||
| memc.h | ||
| sa1111.h | ||
| scoop.h | ||
| ssp.h | ||
| timer-sp.h | ||