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e074f98032
Add detection support for the S3C6400 SoC which has it's id register in a different place to the S3C6410. Signed-off-by: Ben Dooks <ben-linux@fluff.org>
147 lines
3.4 KiB
C
147 lines
3.4 KiB
C
/* linux/arch/arm/plat-s3c64xx/cpu.c
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*
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* Copyright 2008 Openmoko, Inc.
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* Copyright 2008 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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* http://armlinux.simtec.co.uk/
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*
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* S3C64XX CPU Support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/sysdev.h>
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#include <linux/serial_core.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <mach/hardware.h>
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#include <mach/map.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <plat/regs-serial.h>
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#include <plat/cpu.h>
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#include <plat/devs.h>
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#include <plat/clock.h>
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#include <plat/s3c6400.h>
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#include <plat/s3c6410.h>
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/* table of supported CPUs */
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static const char name_s3c6400[] = "S3C6400";
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static const char name_s3c6410[] = "S3C6410";
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static struct cpu_table cpu_ids[] __initdata = {
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{
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.idcode = 0x36400000,
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.idmask = 0xfffff000,
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.map_io = s3c6400_map_io,
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.init_clocks = s3c6400_init_clocks,
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.init_uarts = s3c6400_init_uarts,
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.init = s3c6400_init,
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.name = name_s3c6400,
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}, {
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.idcode = 0x36410100,
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.idmask = 0xffffff00,
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.map_io = s3c6410_map_io,
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.init_clocks = s3c6410_init_clocks,
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.init_uarts = s3c6410_init_uarts,
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.init = s3c6410_init,
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.name = name_s3c6410,
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},
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};
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/* minimal IO mapping */
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/* see notes on uart map in arch/arm/mach-s3c6400/include/mach/debug-macro.S */
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#define UART_OFFS (S3C_PA_UART & 0xfffff)
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static struct map_desc s3c_iodesc[] __initdata = {
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{
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.virtual = (unsigned long)S3C_VA_SYS,
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.pfn = __phys_to_pfn(S3C64XX_PA_SYSCON),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)(S3C_VA_UART + UART_OFFS),
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.pfn = __phys_to_pfn(S3C_PA_UART),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S3C_VA_VIC0,
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.pfn = __phys_to_pfn(S3C64XX_PA_VIC0),
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.length = SZ_16K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S3C_VA_VIC1,
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.pfn = __phys_to_pfn(S3C64XX_PA_VIC1),
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.length = SZ_16K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S3C_VA_TIMER,
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.pfn = __phys_to_pfn(S3C_PA_TIMER),
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.length = SZ_16K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S3C64XX_VA_GPIO,
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.pfn = __phys_to_pfn(S3C64XX_PA_GPIO),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = (unsigned long)S3C64XX_VA_MODEM,
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.pfn = __phys_to_pfn(S3C64XX_PA_MODEM),
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.length = SZ_4K,
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.type = MT_DEVICE,
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},
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};
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struct sysdev_class s3c64xx_sysclass = {
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.name = "s3c64xx-core",
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};
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static struct sys_device s3c64xx_sysdev = {
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.cls = &s3c64xx_sysclass,
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};
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/* read cpu identification code */
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void __init s3c64xx_init_io(struct map_desc *mach_desc, int size)
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{
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unsigned long idcode;
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/* initialise the io descriptors we need for initialisation */
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iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
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iotable_init(mach_desc, size);
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idcode = __raw_readl(S3C_VA_SYS + 0x118);
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if (!idcode) {
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/* S3C6400 has the ID register in a different place,
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* and needs a write before it can be read. */
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__raw_writel(0x0, S3C_VA_SYS + 0xA1C);
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idcode = __raw_readl(S3C_VA_SYS + 0xA1C);
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}
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s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids));
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}
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static __init int s3c64xx_sysdev_init(void)
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{
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sysdev_class_register(&s3c64xx_sysclass);
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return sysdev_register(&s3c64xx_sysdev);
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}
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core_initcall(s3c64xx_sysdev_init);
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