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0978e95253
Add PCIE bindings for the Amlogic G12A SoC, the support is the same but the PHY is shared with USB3 to control the differential lines. Thus this adds a phy phandle to control the PHY, and only requires the MIPI clock for the Amlogic AXG SoC Family. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Andrew Murray <andrew.murray@arm.com>
75 lines
2.4 KiB
Plaintext
75 lines
2.4 KiB
Plaintext
Amlogic Meson AXG DWC PCIE SoC controller
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Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core.
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It shares common functions with the PCIe DesignWare core driver and
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inherits common properties defined in
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Documentation/devicetree/bindings/pci/designware-pcie.txt.
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Additional properties are described here:
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Required properties:
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- compatible:
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should contain :
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- "amlogic,axg-pcie" for AXG SoC Family
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- "amlogic,g12a-pcie" for G12A SoC Family
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to identify the core.
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- reg:
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should contain the configuration address space.
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- reg-names: Must be
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- "elbi" External local bus interface registers
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- "cfg" Meson specific registers
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- "phy" Meson PCIE PHY registers for AXG SoC Family
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- "config" PCIe configuration space
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- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal.
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- clocks: Must contain an entry for each entry in clock-names.
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- clock-names: Must include the following entries:
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- "pclk" PCIe GEN 100M PLL clock
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- "port" PCIe_x(A or B) RC clock gate
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- "general" PCIe Phy clock
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- "mipi" PCIe_x(A or B) 100M ref clock gate for AXG SoC Family
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- resets: phandle to the reset lines.
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- reset-names: must contain "phy" "port" and "apb"
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- "phy" Share PHY reset for AXG SoC Family
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- "port" Port A or B reset
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- "apb" Share APB reset
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- phys: should contain a phandle to the shared phy for G12A SoC Family
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- device_type:
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should be "pci". As specified in designware-pcie.txt
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Example configuration:
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pcie: pcie@f9800000 {
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compatible = "amlogic,axg-pcie", "snps,dw-pcie";
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reg = <0x0 0xf9800000 0x0 0x400000
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0x0 0xff646000 0x0 0x2000
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0x0 0xff644000 0x0 0x2000
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0x0 0xf9f00000 0x0 0x100000>;
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reg-names = "elbi", "cfg", "phy", "config";
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reset-gpios = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>;
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interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;
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bus-range = <0x0 0xff>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges = <0x82000000 0 0 0x0 0xf9c00000 0 0x00300000>;
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clocks = <&clkc CLKID_USB
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&clkc CLKID_MIPI_ENABLE
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&clkc CLKID_PCIE_A
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&clkc CLKID_PCIE_CML_EN0>;
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clock-names = "general",
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"mipi",
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"pclk",
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"port";
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resets = <&reset RESET_PCIE_PHY>,
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<&reset RESET_PCIE_A>,
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<&reset RESET_PCIE_APB>;
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reset-names = "phy",
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"port",
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"apb";
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};
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