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e16415313c
Currently, all imx pinctrl drivers maintain a big array of struct imx_pin_reg which hard-codes data like register offset and mux mode setting for each pin function. Every time a new imx SoC support is added, we need to add such a big mount of data. With moving to single kernel build, it's only matter of time to be blamed on memory consuming. With DTC pre-processor support in place, the patch moves all these data into device tree by redefining the PIN_FUNC_ID in imxXX-pinfunc.h and changing the PIN_FUNC_ID parsing code a little bit. The pin id gets re-numbered based on mux register offset, or config register offset if the pin has no mux register, so that kernel can identify the pin id from register offsets provided by device tree. As a bonus point of the change, those arbitrary magic numbers standing for particular PIN_FUNC_ID in device tree sources are now replaced by macros to improve the readability of dts files. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Dong Aisheng <dong.aisheng@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> |
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| .. | ||
| allwinner,sunxi-pinctrl.txt | ||
| atmel,at91-pinctrl.txt | ||
| brcm,bcm2835-gpio.txt | ||
| fsl,imx6q-pinctrl.txt | ||
| fsl,imx35-pinctrl.txt | ||
| fsl,imx51-pinctrl.txt | ||
| fsl,imx53-pinctrl.txt | ||
| fsl,imx-pinctrl.txt | ||
| fsl,mxs-pinctrl.txt | ||
| lantiq,falcon-pinumx.txt | ||
| lantiq,xway-pinumx.txt | ||
| marvell,armada-370-pinctrl.txt | ||
| marvell,armada-xp-pinctrl.txt | ||
| marvell,dove-pinctrl.txt | ||
| marvell,kirkwood-pinctrl.txt | ||
| marvell,mvebu-pinctrl.txt | ||
| nvidia,tegra20-pinmux.txt | ||
| nvidia,tegra30-pinmux.txt | ||
| nvidia,tegra114-pinmux.txt | ||
| pinctrl_spear.txt | ||
| pinctrl-bindings.txt | ||
| pinctrl-single.txt | ||
| pinctrl-sirf.txt | ||
| samsung-pinctrl.txt | ||
| ste,nomadik.txt | ||