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ffb910d7b8
With commit 02b4e2756e ("ARM: v7 setup
function should invalidate L1 cache"), the default secondary_startup
function for ARMv7 CPUs does invalidate the L1 cache, which was the sole
reason why BCM63xx had to have its own secondary_startup implementation.
Now that the secondary_startup takes care of this, we can completely
remove that code.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
170 lines
4.0 KiB
C
170 lines
4.0 KiB
C
/*
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* Broadcom BCM63138 DSL SoCs SMP support code
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*
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* Copyright (C) 2015, Broadcom Corporation
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*
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* Licensed under the terms of the GPLv2
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*/
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/smp.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <asm/cacheflush.h>
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#include <asm/smp_scu.h>
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#include <asm/smp_plat.h>
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#include <asm/vfp.h>
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#include "bcm63xx_smp.h"
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/* Size of mapped Cortex A9 SCU address space */
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#define CORTEX_A9_SCU_SIZE 0x58
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/*
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* Enable the Cortex A9 Snoop Control Unit
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*
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* By the time this is called we already know there are multiple
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* cores present. We assume we're running on a Cortex A9 processor,
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* so any trouble getting the base address register or getting the
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* SCU base is a problem.
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*
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* Return 0 if successful or an error code otherwise.
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*/
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static int __init scu_a9_enable(void)
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{
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unsigned long config_base;
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void __iomem *scu_base;
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unsigned int i, ncores;
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if (!scu_a9_has_base()) {
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pr_err("no configuration base address register!\n");
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return -ENXIO;
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}
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/* Config base address register value is zero for uniprocessor */
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config_base = scu_a9_get_base();
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if (!config_base) {
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pr_err("hardware reports only one core\n");
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return -ENOENT;
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}
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scu_base = ioremap((phys_addr_t)config_base, CORTEX_A9_SCU_SIZE);
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if (!scu_base) {
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pr_err("failed to remap config base (%lu/%u) for SCU\n",
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config_base, CORTEX_A9_SCU_SIZE);
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return -ENOMEM;
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}
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scu_enable(scu_base);
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ncores = scu_base ? scu_get_core_count(scu_base) : 1;
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if (ncores > nr_cpu_ids) {
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pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
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ncores, nr_cpu_ids);
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ncores = nr_cpu_ids;
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}
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/* The BCM63138 SoC has two Cortex-A9 CPUs, CPU0 features a complete
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* and fully functional VFP unit that can be used, but CPU1 does not.
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* Since we will not be able to trap kernel-mode NEON to force
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* migration to CPU0, just do not advertise VFP support at all.
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*
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* This will make vfp_init bail out and do not attempt to use VFP at
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* all, for kernel-mode NEON, we do not want to introduce any
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* conditionals in hot-paths, so we just restrict the system to UP.
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*/
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#ifdef CONFIG_VFP
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if (ncores > 1) {
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pr_warn("SMP: secondary CPUs lack VFP unit, disabling VFP\n");
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vfp_disable();
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#ifdef CONFIG_KERNEL_MODE_NEON
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WARN(1, "SMP: kernel-mode NEON enabled, restricting to UP\n");
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ncores = 1;
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#endif
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}
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#endif
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for (i = 0; i < ncores; i++)
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set_cpu_possible(i, true);
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iounmap(scu_base); /* That's the last we'll need of this */
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return 0;
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}
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static const struct of_device_id bcm63138_bootlut_ids[] = {
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{ .compatible = "brcm,bcm63138-bootlut", },
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{ /* sentinel */ },
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};
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#define BOOTLUT_RESET_VECT 0x20
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static int bcm63138_smp_boot_secondary(unsigned int cpu,
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struct task_struct *idle)
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{
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void __iomem *bootlut_base;
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struct device_node *dn;
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int ret = 0;
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u32 val;
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dn = of_find_matching_node(NULL, bcm63138_bootlut_ids);
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if (!dn) {
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pr_err("SMP: unable to find bcm63138 boot LUT node\n");
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return -ENODEV;
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}
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bootlut_base = of_iomap(dn, 0);
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of_node_put(dn);
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if (!bootlut_base) {
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pr_err("SMP: unable to remap boot LUT base register\n");
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return -ENOMEM;
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}
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/* Locate the secondary CPU node */
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dn = of_get_cpu_node(cpu, NULL);
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if (!dn) {
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pr_err("SMP: failed to locate secondary CPU%d node\n", cpu);
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ret = -ENODEV;
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goto out;
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}
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/* Write the secondary init routine to the BootLUT reset vector */
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val = virt_to_phys(secondary_startup);
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writel_relaxed(val, bootlut_base + BOOTLUT_RESET_VECT);
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/* Power up the core, will jump straight to its reset vector when we
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* return
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*/
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ret = bcm63xx_pmb_power_on_cpu(dn);
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if (ret)
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goto out;
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out:
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iounmap(bootlut_base);
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return ret;
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}
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static void __init bcm63138_smp_prepare_cpus(unsigned int max_cpus)
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{
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int ret;
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ret = scu_a9_enable();
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if (ret) {
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pr_warn("SMP: Cortex-A9 SCU setup failed\n");
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return;
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}
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}
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struct smp_operations bcm63138_smp_ops __initdata = {
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.smp_prepare_cpus = bcm63138_smp_prepare_cpus,
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.smp_boot_secondary = bcm63138_smp_boot_secondary,
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};
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CPU_METHOD_OF_DECLARE(bcm63138_smp, "brcm,bcm63138", &bcm63138_smp_ops);
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