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The CSI dphy found for example on the rk3326/px30 and rk3368 is based on an IP design from Innosilicon. Add a driver for it. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Link: https://lore.kernel.org/r/20210610212935.3520341-3-heiko@sntech.de Signed-off-by: Vinod Koul <vkoul@kernel.org>
460 lines
13 KiB
C
460 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Rockchip MIPI RX Innosilicon DPHY driver
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*
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* Copyright (C) 2021 Fuzhou Rockchip Electronics Co., Ltd.
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/phy/phy.h>
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#include <linux/phy/phy-mipi-dphy.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <linux/reset.h>
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/* GRF */
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#define RK1808_GRF_PD_VI_CON_OFFSET 0x0430
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#define RK3326_GRF_PD_VI_CON_OFFSET 0x0430
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#define RK3368_GRF_SOC_CON6_OFFSET 0x0418
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/* PHY */
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#define CSIDPHY_CTRL_LANE_ENABLE 0x00
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#define CSIDPHY_CTRL_LANE_ENABLE_CK BIT(6)
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#define CSIDPHY_CTRL_LANE_ENABLE_MASK GENMASK(5, 2)
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#define CSIDPHY_CTRL_LANE_ENABLE_UNDEFINED BIT(0)
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/* not present on all variants */
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#define CSIDPHY_CTRL_PWRCTL 0x04
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#define CSIDPHY_CTRL_PWRCTL_UNDEFINED GENMASK(7, 5)
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#define CSIDPHY_CTRL_PWRCTL_SYNCRST BIT(2)
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#define CSIDPHY_CTRL_PWRCTL_LDO_PD BIT(1)
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#define CSIDPHY_CTRL_PWRCTL_PLL_PD BIT(0)
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#define CSIDPHY_CTRL_DIG_RST 0x80
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#define CSIDPHY_CTRL_DIG_RST_UNDEFINED 0x1e
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#define CSIDPHY_CTRL_DIG_RST_RESET BIT(0)
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/* offset after ths_settle_offset */
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#define CSIDPHY_CLK_THS_SETTLE 0
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#define CSIDPHY_LANE_THS_SETTLE(n) (((n) + 1) * 0x80)
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#define CSIDPHY_THS_SETTLE_MASK GENMASK(6, 0)
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/* offset after calib_offset */
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#define CSIDPHY_CLK_CALIB_EN 0
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#define CSIDPHY_LANE_CALIB_EN(n) (((n) + 1) * 0x80)
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#define CSIDPHY_CALIB_EN BIT(7)
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/* Configure the count time of the THS-SETTLE by protocol. */
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#define RK1808_CSIDPHY_CLK_WR_THS_SETTLE 0x160
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#define RK3326_CSIDPHY_CLK_WR_THS_SETTLE 0x100
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#define RK3368_CSIDPHY_CLK_WR_THS_SETTLE 0x100
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/* Calibration reception enable */
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#define RK1808_CSIDPHY_CLK_CALIB_EN 0x168
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/*
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* The higher 16-bit of this register is used for write protection
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* only if BIT(x + 16) set to 1 the BIT(x) can be written.
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*/
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#define HIWORD_UPDATE(val, mask, shift) \
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((val) << (shift) | (mask) << ((shift) + 16))
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#define HZ_TO_MHZ(freq) div_u64(freq, 1000 * 1000)
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enum dphy_reg_id {
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/* rk1808 & rk3326 */
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GRF_DPHY_CSIPHY_FORCERXMODE,
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GRF_DPHY_CSIPHY_CLKLANE_EN,
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GRF_DPHY_CSIPHY_DATALANE_EN,
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};
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struct dphy_reg {
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u32 offset;
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u32 mask;
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u32 shift;
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};
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#define PHY_REG(_offset, _width, _shift) \
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{ .offset = _offset, .mask = BIT(_width) - 1, .shift = _shift, }
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static const struct dphy_reg rk1808_grf_dphy_regs[] = {
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[GRF_DPHY_CSIPHY_FORCERXMODE] = PHY_REG(RK1808_GRF_PD_VI_CON_OFFSET, 4, 0),
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[GRF_DPHY_CSIPHY_CLKLANE_EN] = PHY_REG(RK1808_GRF_PD_VI_CON_OFFSET, 1, 8),
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[GRF_DPHY_CSIPHY_DATALANE_EN] = PHY_REG(RK1808_GRF_PD_VI_CON_OFFSET, 4, 4),
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};
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static const struct dphy_reg rk3326_grf_dphy_regs[] = {
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[GRF_DPHY_CSIPHY_FORCERXMODE] = PHY_REG(RK3326_GRF_PD_VI_CON_OFFSET, 4, 0),
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[GRF_DPHY_CSIPHY_CLKLANE_EN] = PHY_REG(RK3326_GRF_PD_VI_CON_OFFSET, 1, 8),
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[GRF_DPHY_CSIPHY_DATALANE_EN] = PHY_REG(RK3326_GRF_PD_VI_CON_OFFSET, 4, 4),
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};
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static const struct dphy_reg rk3368_grf_dphy_regs[] = {
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[GRF_DPHY_CSIPHY_FORCERXMODE] = PHY_REG(RK3368_GRF_SOC_CON6_OFFSET, 4, 8),
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};
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struct hsfreq_range {
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u32 range_h;
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u8 cfg_bit;
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};
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struct dphy_drv_data {
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int pwrctl_offset;
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int ths_settle_offset;
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int calib_offset;
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const struct hsfreq_range *hsfreq_ranges;
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int num_hsfreq_ranges;
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const struct dphy_reg *grf_regs;
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};
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struct rockchip_inno_csidphy {
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struct device *dev;
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void __iomem *phy_base;
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struct clk *pclk;
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struct regmap *grf;
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struct reset_control *rst;
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const struct dphy_drv_data *drv_data;
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struct phy_configure_opts_mipi_dphy config;
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u8 hsfreq;
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};
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static inline void write_grf_reg(struct rockchip_inno_csidphy *priv,
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int index, u8 value)
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{
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const struct dphy_drv_data *drv_data = priv->drv_data;
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const struct dphy_reg *reg = &drv_data->grf_regs[index];
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if (reg->offset)
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regmap_write(priv->grf, reg->offset,
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HIWORD_UPDATE(value, reg->mask, reg->shift));
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}
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/* These tables must be sorted by .range_h ascending. */
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static const struct hsfreq_range rk1808_mipidphy_hsfreq_ranges[] = {
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{ 109, 0x02}, { 149, 0x03}, { 199, 0x06}, { 249, 0x06},
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{ 299, 0x06}, { 399, 0x08}, { 499, 0x0b}, { 599, 0x0e},
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{ 699, 0x10}, { 799, 0x12}, { 999, 0x16}, {1199, 0x1e},
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{1399, 0x23}, {1599, 0x2d}, {1799, 0x32}, {1999, 0x37},
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{2199, 0x3c}, {2399, 0x41}, {2499, 0x46}
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};
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static const struct hsfreq_range rk3326_mipidphy_hsfreq_ranges[] = {
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{ 109, 0x00}, { 149, 0x01}, { 199, 0x02}, { 249, 0x03},
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{ 299, 0x04}, { 399, 0x05}, { 499, 0x06}, { 599, 0x07},
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{ 699, 0x08}, { 799, 0x09}, { 899, 0x0a}, {1099, 0x0b},
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{1249, 0x0c}, {1349, 0x0d}, {1500, 0x0e}
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};
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static const struct hsfreq_range rk3368_mipidphy_hsfreq_ranges[] = {
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{ 109, 0x00}, { 149, 0x01}, { 199, 0x02}, { 249, 0x03},
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{ 299, 0x04}, { 399, 0x05}, { 499, 0x06}, { 599, 0x07},
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{ 699, 0x08}, { 799, 0x09}, { 899, 0x0a}, {1099, 0x0b},
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{1249, 0x0c}, {1349, 0x0d}, {1500, 0x0e}
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};
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static void rockchip_inno_csidphy_ths_settle(struct rockchip_inno_csidphy *priv,
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int hsfreq, int offset)
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{
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const struct dphy_drv_data *drv_data = priv->drv_data;
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u32 val;
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val = readl(priv->phy_base + drv_data->ths_settle_offset + offset);
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val &= ~CSIDPHY_THS_SETTLE_MASK;
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val |= hsfreq;
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writel(val, priv->phy_base + drv_data->ths_settle_offset + offset);
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}
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static int rockchip_inno_csidphy_configure(struct phy *phy,
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union phy_configure_opts *opts)
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{
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struct rockchip_inno_csidphy *priv = phy_get_drvdata(phy);
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const struct dphy_drv_data *drv_data = priv->drv_data;
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struct phy_configure_opts_mipi_dphy *config = &opts->mipi_dphy;
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unsigned int hsfreq = 0;
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unsigned int i;
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u64 data_rate_mbps;
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int ret;
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/* pass with phy_mipi_dphy_get_default_config (with pixel rate?) */
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ret = phy_mipi_dphy_config_validate(config);
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if (ret)
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return ret;
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data_rate_mbps = HZ_TO_MHZ(config->hs_clk_rate);
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dev_dbg(priv->dev, "lanes %d - data_rate_mbps %llu\n",
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config->lanes, data_rate_mbps);
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for (i = 0; i < drv_data->num_hsfreq_ranges; i++) {
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if (drv_data->hsfreq_ranges[i].range_h >= data_rate_mbps) {
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hsfreq = drv_data->hsfreq_ranges[i].cfg_bit;
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break;
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}
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}
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if (!hsfreq)
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return -EINVAL;
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priv->hsfreq = hsfreq;
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priv->config = *config;
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return 0;
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}
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static int rockchip_inno_csidphy_power_on(struct phy *phy)
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{
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struct rockchip_inno_csidphy *priv = phy_get_drvdata(phy);
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const struct dphy_drv_data *drv_data = priv->drv_data;
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u64 data_rate_mbps = HZ_TO_MHZ(priv->config.hs_clk_rate);
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u32 val;
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int ret, i;
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ret = clk_enable(priv->pclk);
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if (ret < 0)
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return ret;
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ret = pm_runtime_resume_and_get(priv->dev);
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if (ret < 0) {
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clk_disable(priv->pclk);
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return ret;
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}
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/* phy start */
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if (drv_data->pwrctl_offset >= 0)
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writel(CSIDPHY_CTRL_PWRCTL_UNDEFINED |
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CSIDPHY_CTRL_PWRCTL_SYNCRST,
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priv->phy_base + drv_data->pwrctl_offset);
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/* set data lane num and enable clock lane */
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val = FIELD_PREP(CSIDPHY_CTRL_LANE_ENABLE_MASK, GENMASK(priv->config.lanes - 1, 0)) |
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FIELD_PREP(CSIDPHY_CTRL_LANE_ENABLE_CK, 1) |
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FIELD_PREP(CSIDPHY_CTRL_LANE_ENABLE_UNDEFINED, 1);
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writel(val, priv->phy_base + CSIDPHY_CTRL_LANE_ENABLE);
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/* Reset dphy analog part */
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if (drv_data->pwrctl_offset >= 0)
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writel(CSIDPHY_CTRL_PWRCTL_UNDEFINED,
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priv->phy_base + drv_data->pwrctl_offset);
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usleep_range(500, 1000);
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/* Reset dphy digital part */
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writel(CSIDPHY_CTRL_DIG_RST_UNDEFINED,
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priv->phy_base + CSIDPHY_CTRL_DIG_RST);
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writel(CSIDPHY_CTRL_DIG_RST_UNDEFINED + CSIDPHY_CTRL_DIG_RST_RESET,
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priv->phy_base + CSIDPHY_CTRL_DIG_RST);
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/* not into receive mode/wait stopstate */
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write_grf_reg(priv, GRF_DPHY_CSIPHY_FORCERXMODE, 0x0);
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/* enable calibration */
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if (data_rate_mbps > 1500 && drv_data->calib_offset >= 0) {
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writel(CSIDPHY_CALIB_EN,
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priv->phy_base + drv_data->calib_offset +
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CSIDPHY_CLK_CALIB_EN);
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for (i = 0; i < priv->config.lanes; i++)
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writel(CSIDPHY_CALIB_EN,
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priv->phy_base + drv_data->calib_offset +
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CSIDPHY_LANE_CALIB_EN(i));
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}
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rockchip_inno_csidphy_ths_settle(priv, priv->hsfreq,
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CSIDPHY_CLK_THS_SETTLE);
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for (i = 0; i < priv->config.lanes; i++)
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rockchip_inno_csidphy_ths_settle(priv, priv->hsfreq,
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CSIDPHY_LANE_THS_SETTLE(i));
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write_grf_reg(priv, GRF_DPHY_CSIPHY_CLKLANE_EN, 0x1);
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write_grf_reg(priv, GRF_DPHY_CSIPHY_DATALANE_EN,
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GENMASK(priv->config.lanes - 1, 0));
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return 0;
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}
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static int rockchip_inno_csidphy_power_off(struct phy *phy)
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{
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struct rockchip_inno_csidphy *priv = phy_get_drvdata(phy);
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const struct dphy_drv_data *drv_data = priv->drv_data;
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/* disable all lanes */
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writel(CSIDPHY_CTRL_LANE_ENABLE_UNDEFINED,
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priv->phy_base + CSIDPHY_CTRL_LANE_ENABLE);
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/* disable pll and ldo */
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if (drv_data->pwrctl_offset >= 0)
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writel(CSIDPHY_CTRL_PWRCTL_UNDEFINED |
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CSIDPHY_CTRL_PWRCTL_LDO_PD |
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CSIDPHY_CTRL_PWRCTL_PLL_PD,
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priv->phy_base + drv_data->pwrctl_offset);
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usleep_range(500, 1000);
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pm_runtime_put(priv->dev);
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clk_disable(priv->pclk);
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return 0;
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}
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static int rockchip_inno_csidphy_init(struct phy *phy)
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{
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struct rockchip_inno_csidphy *priv = phy_get_drvdata(phy);
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return clk_prepare(priv->pclk);
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}
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static int rockchip_inno_csidphy_exit(struct phy *phy)
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{
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struct rockchip_inno_csidphy *priv = phy_get_drvdata(phy);
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clk_unprepare(priv->pclk);
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return 0;
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}
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static const struct phy_ops rockchip_inno_csidphy_ops = {
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.power_on = rockchip_inno_csidphy_power_on,
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.power_off = rockchip_inno_csidphy_power_off,
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.init = rockchip_inno_csidphy_init,
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.exit = rockchip_inno_csidphy_exit,
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.configure = rockchip_inno_csidphy_configure,
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.owner = THIS_MODULE,
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};
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static const struct dphy_drv_data rk1808_mipidphy_drv_data = {
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.pwrctl_offset = -1,
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.ths_settle_offset = RK1808_CSIDPHY_CLK_WR_THS_SETTLE,
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.calib_offset = RK1808_CSIDPHY_CLK_CALIB_EN,
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.hsfreq_ranges = rk1808_mipidphy_hsfreq_ranges,
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.num_hsfreq_ranges = ARRAY_SIZE(rk1808_mipidphy_hsfreq_ranges),
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.grf_regs = rk1808_grf_dphy_regs,
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};
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static const struct dphy_drv_data rk3326_mipidphy_drv_data = {
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.pwrctl_offset = CSIDPHY_CTRL_PWRCTL,
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.ths_settle_offset = RK3326_CSIDPHY_CLK_WR_THS_SETTLE,
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.calib_offset = -1,
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.hsfreq_ranges = rk3326_mipidphy_hsfreq_ranges,
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.num_hsfreq_ranges = ARRAY_SIZE(rk3326_mipidphy_hsfreq_ranges),
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.grf_regs = rk3326_grf_dphy_regs,
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};
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static const struct dphy_drv_data rk3368_mipidphy_drv_data = {
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.pwrctl_offset = CSIDPHY_CTRL_PWRCTL,
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.ths_settle_offset = RK3368_CSIDPHY_CLK_WR_THS_SETTLE,
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.calib_offset = -1,
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.hsfreq_ranges = rk3368_mipidphy_hsfreq_ranges,
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.num_hsfreq_ranges = ARRAY_SIZE(rk3368_mipidphy_hsfreq_ranges),
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.grf_regs = rk3368_grf_dphy_regs,
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};
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static const struct of_device_id rockchip_inno_csidphy_match_id[] = {
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{
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.compatible = "rockchip,px30-csi-dphy",
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.data = &rk3326_mipidphy_drv_data,
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},
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{
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.compatible = "rockchip,rk1808-csi-dphy",
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.data = &rk1808_mipidphy_drv_data,
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},
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{
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.compatible = "rockchip,rk3326-csi-dphy",
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.data = &rk3326_mipidphy_drv_data,
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},
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{
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.compatible = "rockchip,rk3368-csi-dphy",
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.data = &rk3368_mipidphy_drv_data,
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},
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{}
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};
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MODULE_DEVICE_TABLE(of, rockchip_inno_csidphy_match_id);
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static int rockchip_inno_csidphy_probe(struct platform_device *pdev)
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{
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struct rockchip_inno_csidphy *priv;
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struct device *dev = &pdev->dev;
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struct phy_provider *phy_provider;
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struct phy *phy;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->dev = dev;
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platform_set_drvdata(pdev, priv);
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priv->drv_data = of_device_get_match_data(dev);
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if (!priv->drv_data) {
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dev_err(dev, "Can't find device data\n");
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return -ENODEV;
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}
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priv->grf = syscon_regmap_lookup_by_phandle(dev->of_node,
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"rockchip,grf");
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if (IS_ERR(priv->grf)) {
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dev_err(dev, "Can't find GRF syscon\n");
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return PTR_ERR(priv->grf);
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}
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priv->phy_base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(priv->phy_base))
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return PTR_ERR(priv->phy_base);
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priv->pclk = devm_clk_get(dev, "pclk");
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if (IS_ERR(priv->pclk)) {
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dev_err(dev, "failed to get pclk\n");
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return PTR_ERR(priv->pclk);
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}
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priv->rst = devm_reset_control_get(dev, "apb");
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if (IS_ERR(priv->rst)) {
|
|
dev_err(dev, "failed to get system reset control\n");
|
|
return PTR_ERR(priv->rst);
|
|
}
|
|
|
|
phy = devm_phy_create(dev, NULL, &rockchip_inno_csidphy_ops);
|
|
if (IS_ERR(phy)) {
|
|
dev_err(dev, "failed to create phy\n");
|
|
return PTR_ERR(phy);
|
|
}
|
|
|
|
phy_set_drvdata(phy, priv);
|
|
|
|
phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
|
|
if (IS_ERR(phy_provider)) {
|
|
dev_err(dev, "failed to register phy provider\n");
|
|
return PTR_ERR(phy_provider);
|
|
}
|
|
|
|
pm_runtime_enable(dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int rockchip_inno_csidphy_remove(struct platform_device *pdev)
|
|
{
|
|
struct rockchip_inno_csidphy *priv = platform_get_drvdata(pdev);
|
|
|
|
pm_runtime_disable(priv->dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver rockchip_inno_csidphy_driver = {
|
|
.driver = {
|
|
.name = "rockchip-inno-csidphy",
|
|
.of_match_table = rockchip_inno_csidphy_match_id,
|
|
},
|
|
.probe = rockchip_inno_csidphy_probe,
|
|
.remove = rockchip_inno_csidphy_remove,
|
|
};
|
|
|
|
module_platform_driver(rockchip_inno_csidphy_driver);
|
|
MODULE_AUTHOR("Heiko Stuebner <heiko.stuebner@theobroma-systems.com>");
|
|
MODULE_DESCRIPTION("Rockchip MIPI Innosilicon CSI-DPHY driver");
|
|
MODULE_LICENSE("GPL v2");
|