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This patch allows the IPU to divide the 27 MHz input clock from the TVE by two to obtain the 13.5 MHz pixel clock needed for NTSC/PAL SD modes. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> |
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drm | ||
host1x | ||
ipu-v3 | ||
vga | ||
Makefile |