linux/drivers/clk/tegra
Jon Hunter c461c677a8 clk: tegra: Fix Tegra PWM parent clock
Commit 8c193f4714 ("pwm: tegra: Optimize period calculation") updated
the period calculation in the Tegra PWM driver and now returns an error
if the period requested is less than minimum period supported. This is
breaking PWM support on various Tegra platforms. For example, on the
Tegra210 Jetson Nano platform this is breaking the PWM fan support and
probing the PWM fan driver now fails ...

 pwm-fan pwm-fan: Failed to configure PWM: -22
 pwm-fan: probe of pwm-fan failed with error -22

The problem is that the default parent clock for the PWM on Tegra210 is
a 32kHz clock and is unable to support the requested PWM period.

Fix PWM support on Tegra20, Tegra30, Tegra114, Tegra124 and Tegra210 by
updating the parent clock for the PWM to be the PLL_P.

Fixes: 8c193f4714 ("pwm: tegra: Optimize period calculation")
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # TF101 T20
Tested-by: Antoni Aloy Torrens <aaloytorrens@gmail.com> # TF101 T20
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # TF201 T30
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # TF700T T3
Link: https://lore.kernel.org/r/20221010100046.6477-1-jonathanh@nvidia.com
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-10-14 13:44:24 -07:00
..
clk-audio-sync.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201 2019-05-30 11:29:52 -07:00
clk-bpmp.c clk: move from strlcpy with unused retval to strscpy 2022-08-22 16:22:53 -07:00
clk-device.c clk: tegra: Support runtime PM and power domain 2021-12-15 18:55:21 +01:00
clk-dfll.c clk: tegra: Update kerneldoc to match prototypes 2022-05-06 10:56:00 +02:00
clk-dfll.h clk: tegra: clk-dfll: Add suspend and resume support 2019-11-11 14:53:03 +01:00
clk-divider.c clk: tegra: divider: Check UART's divider enable-bit state on rate's recalculation 2020-01-10 15:50:05 +01:00
clk-id.h clk: tegra: Fix duplicated SE clock entry 2020-12-10 12:51:59 -08:00
clk-periph-fixed.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201 2019-05-30 11:29:52 -07:00
clk-periph-gate.c clk: tegra: Don't deassert reset on enabling clocks 2021-05-31 15:16:46 +02:00
clk-periph.c clk: tegra: Fix refcounting of gate clocks 2021-05-31 15:16:24 +02:00
clk-pll-out.c clk: tegra: pllout: Save and restore pllout context 2019-11-11 14:53:02 +01:00
clk-pll.c clk: tegra: Support runtime PM and power domain 2021-12-15 18:55:21 +01:00
clk-sdmmc-mux.c clk: tegra: Implement disable_unused() of tegra_clk_sdmmc_mux_ops 2021-07-27 14:54:19 -07:00
clk-super.c clk: tegra: Support runtime PM and power domain 2021-12-15 18:55:21 +01:00
clk-tegra20-emc.c clk: tegra: Export Tegra20 EMC kernel symbols 2020-11-06 19:24:04 +01:00
clk-tegra20.c clk: tegra: Fix Tegra PWM parent clock 2022-10-14 13:44:24 -07:00
clk-tegra30.c clk: tegra: Fix Tegra PWM parent clock 2022-10-14 13:44:24 -07:00
clk-tegra114.c clk: tegra: Fix Tegra PWM parent clock 2022-10-14 13:44:24 -07:00
clk-tegra124-dfll-fcpu.c clk: tegra: clk-tegra124-dfll-fcpu: don't use devm functions for regulator 2021-06-25 16:23:07 -07:00
clk-tegra124-emc.c clk: tegra: tegra124-emc: Fix missing put_device() call in emc_ensure_emc_driver 2022-03-11 19:22:18 -08:00
clk-tegra124.c clk: tegra: Fix Tegra PWM parent clock 2022-10-14 13:44:24 -07:00
clk-tegra210-emc.c This pull request contains zero diff to the core framework. It is a collection 2020-10-22 12:53:28 -07:00
clk-tegra210.c clk: tegra: Fix Tegra PWM parent clock 2022-10-14 13:44:24 -07:00
clk-tegra-audio.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201 2019-05-30 11:29:52 -07:00
clk-tegra-fixed.c clk: tegra: Remove CLK_M_DIV fixed clocks 2020-03-12 11:33:32 +01:00
clk-tegra-periph.c clk: tegra: Remove CLK_IS_CRITICAL flag from fuse clock 2021-08-11 11:57:01 +02:00
clk-tegra-super-cclk.c clk: tegra: cclk: Handle thermal DIV2 CPU frequency throttling 2021-05-31 15:16:26 +02:00
clk-tegra-super-gen4.c clk: tegra: clk-super: Fix to enable PLLP branches to CPU 2019-11-11 14:53:03 +01:00
clk-utils.c clk: tegra: Refactor fractional divider calculation 2018-07-25 13:43:34 -07:00
clk.c clk: tegra: Support runtime PM and power domain 2021-12-15 18:55:21 +01:00
clk.h clk: tegra: Support runtime PM and power domain 2021-12-15 18:55:21 +01:00
cvb.c clk: tegra: cvb: Provide missing description for 'tegra_cvb_add_opp_table()'s align param 2021-02-11 11:56:05 -08:00
cvb.h treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174 2019-05-30 11:26:41 -07:00
Kconfig memory: tegra124-emc: Make driver modular 2021-01-05 18:00:09 +01:00
Makefile clk: tegra: Support runtime PM and power domain 2021-12-15 18:55:21 +01:00