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252 lines
6.8 KiB
C
252 lines
6.8 KiB
C
/*
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* Copyright © 2008 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Keith Packard <keithp@keithp.com>
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*
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*/
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#include "drmP.h"
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#include "drm.h"
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#include "i915_drm.h"
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#include "i915_drv.h"
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#if WATCH_LISTS
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int
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i915_verify_lists(struct drm_device *dev)
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{
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static int warned;
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drm_i915_private_t *dev_priv = dev->dev_private;
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struct drm_i915_gem_object *obj;
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int err = 0;
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if (warned)
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return 0;
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list_for_each_entry(obj, &dev_priv->render_ring.active_list, list) {
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if (obj->base.dev != dev ||
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!atomic_read(&obj->base.refcount.refcount)) {
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DRM_ERROR("freed render active %p\n", obj);
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err++;
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break;
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} else if (!obj->active ||
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(obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) {
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DRM_ERROR("invalid render active %p (a %d r %x)\n",
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obj,
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obj->active,
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obj->base.read_domains);
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err++;
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} else if (obj->base.write_domain && list_empty(&obj->gpu_write_list)) {
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DRM_ERROR("invalid render active %p (w %x, gwl %d)\n",
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obj,
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obj->base.write_domain,
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!list_empty(&obj->gpu_write_list));
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err++;
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}
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}
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list_for_each_entry(obj, &dev_priv->mm.flushing_list, list) {
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if (obj->base.dev != dev ||
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!atomic_read(&obj->base.refcount.refcount)) {
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DRM_ERROR("freed flushing %p\n", obj);
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err++;
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break;
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} else if (!obj->active ||
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(obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0 ||
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list_empty(&obj->gpu_write_list)){
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DRM_ERROR("invalid flushing %p (a %d w %x gwl %d)\n",
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obj,
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obj->active,
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obj->base.write_domain,
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!list_empty(&obj->gpu_write_list));
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err++;
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}
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}
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list_for_each_entry(obj, &dev_priv->mm.gpu_write_list, gpu_write_list) {
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if (obj->base.dev != dev ||
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!atomic_read(&obj->base.refcount.refcount)) {
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DRM_ERROR("freed gpu write %p\n", obj);
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err++;
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break;
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} else if (!obj->active ||
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(obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0) {
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DRM_ERROR("invalid gpu write %p (a %d w %x)\n",
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obj,
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obj->active,
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obj->base.write_domain);
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err++;
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}
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}
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list_for_each_entry(obj, &dev_priv->mm.inactive_list, list) {
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if (obj->base.dev != dev ||
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!atomic_read(&obj->base.refcount.refcount)) {
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DRM_ERROR("freed inactive %p\n", obj);
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err++;
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break;
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} else if (obj->pin_count || obj->active ||
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(obj->base.write_domain & I915_GEM_GPU_DOMAINS)) {
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DRM_ERROR("invalid inactive %p (p %d a %d w %x)\n",
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obj,
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obj->pin_count, obj->active,
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obj->base.write_domain);
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err++;
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}
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}
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list_for_each_entry(obj, &dev_priv->mm.pinned_list, list) {
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if (obj->base.dev != dev ||
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!atomic_read(&obj->base.refcount.refcount)) {
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DRM_ERROR("freed pinned %p\n", obj);
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err++;
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break;
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} else if (!obj->pin_count || obj->active ||
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(obj->base.write_domain & I915_GEM_GPU_DOMAINS)) {
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DRM_ERROR("invalid pinned %p (p %d a %d w %x)\n",
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obj,
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obj->pin_count, obj->active,
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obj->base.write_domain);
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err++;
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}
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}
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return warned = err;
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}
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#endif /* WATCH_INACTIVE */
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#if WATCH_EXEC | WATCH_PWRITE
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static void
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i915_gem_dump_page(struct page *page, uint32_t start, uint32_t end,
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uint32_t bias, uint32_t mark)
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{
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uint32_t *mem = kmap_atomic(page, KM_USER0);
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int i;
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for (i = start; i < end; i += 4)
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DRM_INFO("%08x: %08x%s\n",
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(int) (bias + i), mem[i / 4],
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(bias + i == mark) ? " ********" : "");
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kunmap_atomic(mem, KM_USER0);
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/* give syslog time to catch up */
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msleep(1);
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}
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void
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i915_gem_dump_object(struct drm_gem_object *obj, int len,
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const char *where, uint32_t mark)
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{
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struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
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int page;
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DRM_INFO("%s: object at offset %08x\n", where, obj_priv->gtt_offset);
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for (page = 0; page < (len + PAGE_SIZE-1) / PAGE_SIZE; page++) {
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int page_len, chunk, chunk_len;
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page_len = len - page * PAGE_SIZE;
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if (page_len > PAGE_SIZE)
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page_len = PAGE_SIZE;
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for (chunk = 0; chunk < page_len; chunk += 128) {
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chunk_len = page_len - chunk;
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if (chunk_len > 128)
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chunk_len = 128;
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i915_gem_dump_page(obj_priv->pages[page],
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chunk, chunk + chunk_len,
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obj_priv->gtt_offset +
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page * PAGE_SIZE,
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mark);
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}
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}
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}
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#endif
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#if WATCH_COHERENCY
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void
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i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle)
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{
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struct drm_device *dev = obj->dev;
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struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
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int page;
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uint32_t *gtt_mapping;
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uint32_t *backing_map = NULL;
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int bad_count = 0;
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DRM_INFO("%s: checking coherency of object %p@0x%08x (%d, %zdkb):\n",
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__func__, obj, obj_priv->gtt_offset, handle,
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obj->size / 1024);
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gtt_mapping = ioremap(dev->agp->base + obj_priv->gtt_offset,
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obj->size);
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if (gtt_mapping == NULL) {
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DRM_ERROR("failed to map GTT space\n");
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return;
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}
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for (page = 0; page < obj->size / PAGE_SIZE; page++) {
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int i;
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backing_map = kmap_atomic(obj_priv->pages[page], KM_USER0);
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if (backing_map == NULL) {
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DRM_ERROR("failed to map backing page\n");
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goto out;
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}
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for (i = 0; i < PAGE_SIZE / 4; i++) {
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uint32_t cpuval = backing_map[i];
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uint32_t gttval = readl(gtt_mapping +
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page * 1024 + i);
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if (cpuval != gttval) {
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DRM_INFO("incoherent CPU vs GPU at 0x%08x: "
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"0x%08x vs 0x%08x\n",
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(int)(obj_priv->gtt_offset +
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page * PAGE_SIZE + i * 4),
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cpuval, gttval);
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if (bad_count++ >= 8) {
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DRM_INFO("...\n");
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goto out;
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}
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}
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}
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kunmap_atomic(backing_map, KM_USER0);
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backing_map = NULL;
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}
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out:
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if (backing_map != NULL)
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kunmap_atomic(backing_map, KM_USER0);
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iounmap(gtt_mapping);
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/* give syslog time to catch up */
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msleep(1);
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/* Directly flush the object, since we just loaded values with the CPU
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* from the backing pages and we don't want to disturb the cache
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* management that we're trying to observe.
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*/
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i915_gem_clflush_object(obj);
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}
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#endif
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