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e03f9088e2
Add r8a7779 specific support for IRLM bit configuration in the INTC-IRQPIN driver. Without this code we need special workaround code in arch/arm/mach-shmobile. The IRLM bit for the INTC hardware exists on various older SH-based SoCs and is used to select between two modes for the external interrupt pins IRQ0 to IRQ3: IRLM = 0: (default from reset on r8a7779) In this mode the pins IRQ0 to IRQ3 are used together to give a value between 0 and 15 to the SoC. External logic is required for masking. This mode is not supported by the INTC-IRQPIN driver. IRLM = 1: (needs this patch or configuration elsewhere) In this mode IRQ0 to IRQ3 operate as 4 individual external interrupt pins. In this mode the SMSC ethernet chip can be used via IRQ1 on r8a7779 Marzen. This mode is the only supported mode by the INTC-IRQPIN driver. For this patch to work the r8a7779 DTS needs to pass the ICR0 register as the last register bank. Signed-off-by: Magnus Damm <damm+renesas@opensource.se> Cc: Magnus Damm <magnus.damm@gmail.com> Cc: horms@verge.net.au Cc: jason@lakedaemon.net Link: http://lkml.kernel.org/r/20141203121803.5936.35881.sendpatchset@w520 Signed-off-by: Thomas Gleixner <tglx@linutronix.de> |
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| .. | ||
| abilis,tb10x-ictl.txt | ||
| allwinner,sun4i-ic.txt | ||
| allwinner,sun67i-sc-nmi.txt | ||
| atmel,aic.txt | ||
| brcm,bcm2835-armctrl-ic.txt | ||
| brcm,bcm7120-l2-intc.txt | ||
| brcm,l2-intc.txt | ||
| cirrus,clps711x-intc.txt | ||
| interrupts.txt | ||
| lsi,zevio-intc.txt | ||
| marvell,armada-370-xp-mpic.txt | ||
| marvell,orion-intc.txt | ||
| mips-gic.txt | ||
| opencores,or1k-pic.txt | ||
| renesas,intc-irqpin.txt | ||
| renesas,irqc.txt | ||
| samsung,s3c24xx-irq.txt | ||
| snps,dw-apb-ictl.txt | ||
| ti,keystone-irq.txt | ||