Lad Prabhakar e021ae7f51 riscv: errata: Add Andes alternative ports ... Add required ports of the Alternative scheme for Andes CPU cores. I/O Coherence Port (IOCP) provides an AXI interface for connecting external non-caching masters, such as DMA controllers. IOCP is a specification option and is disabled on the Renesas RZ/Five SoC due to this reason cache management needs a software workaround. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Tested-by: Conor Dooley <conor.dooley@microchip.com> # tyre-kicking on a d1 Link: https://lore.kernel.org/r/20230818135723.80612-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>		2023-09-01 09:08:56 -07:00
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andes	riscv: errata: Add Andes alternative ports	2023-09-01 09:08:56 -07:00
sifive	RISC-V: fix sifive and thead section mismatches in errata	2023-04-29 13:18:19 -07:00
thead	riscv: errata: thead: only set cbom size & noncoherent during boot	2023-07-06 10:32:03 -07:00
Makefile	riscv: errata: Add Andes alternative ports	2023-09-01 09:08:56 -07:00