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Conflicts: arch/arm/mach-spear3xx/clock.c arch/arm/mach-spear3xx/include/mach/generic.h arch/arm/mach-spear3xx/include/mach/misc_regs.h arch/arm/mach-spear3xx/spear320.c arch/arm/mach-spear6xx/clock.c arch/arm/mach-spear6xx/include/mach/misc_regs.h Resolve even more merge conflicts. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
61 lines
2.2 KiB
C
61 lines
2.2 KiB
C
/*
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* arch/arm/mach-spear3xx/include/mach/spear.h
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*
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* SPEAr3xx Machine family specific definition
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*
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* Copyright (C) 2009 ST Microelectronics
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* Viresh Kumar<viresh.kumar@st.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __MACH_SPEAR3XX_H
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#define __MACH_SPEAR3XX_H
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#include <asm/memory.h>
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/* ICM1 - Low speed connection */
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#define SPEAR3XX_ICM1_2_BASE UL(0xD0000000)
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#define VA_SPEAR3XX_ICM1_2_BASE UL(0xFD000000)
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#define SPEAR3XX_ICM1_UART_BASE UL(0xD0000000)
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#define VA_SPEAR3XX_ICM1_UART_BASE (VA_SPEAR3XX_ICM1_2_BASE | SPEAR3XX_ICM1_UART_BASE)
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#define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000)
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/* ML1 - Multi Layer CPU Subsystem */
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#define SPEAR3XX_ICM3_ML1_2_BASE UL(0xF0000000)
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#define VA_SPEAR6XX_ML_CPU_BASE UL(0xF0000000)
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/* ICM3 - Basic Subsystem */
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#define SPEAR3XX_ICM3_SMI_CTRL_BASE UL(0xFC000000)
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#define VA_SPEAR3XX_ICM3_SMI_CTRL_BASE UL(0xFC000000)
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#define SPEAR3XX_ICM3_DMA_BASE UL(0xFC400000)
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#define SPEAR3XX_ICM3_SYS_CTRL_BASE UL(0xFCA00000)
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#define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_SYS_CTRL_BASE)
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#define SPEAR3XX_ICM3_MISC_REG_BASE UL(0xFCA80000)
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#define VA_SPEAR3XX_ICM3_MISC_REG_BASE (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_MISC_REG_BASE)
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/* Debug uart for linux, will be used for debug and uncompress messages */
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#define SPEAR_DBG_UART_BASE SPEAR3XX_ICM1_UART_BASE
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#define VA_SPEAR_DBG_UART_BASE VA_SPEAR3XX_ICM1_UART_BASE
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/* Sysctl base for spear platform */
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#define SPEAR_SYS_CTRL_BASE SPEAR3XX_ICM3_SYS_CTRL_BASE
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#define VA_SPEAR_SYS_CTRL_BASE VA_SPEAR3XX_ICM3_SYS_CTRL_BASE
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/* SPEAr320 Macros */
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#define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000)
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#define VA_SPEAR320_SOC_CONFIG_BASE UL(0xFE000000)
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#define SPEAR320_CONTROL_REG IOMEM(VA_SPEAR320_SOC_CONFIG_BASE)
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#define SPEAR320_EXT_CTRL_REG IOMEM(VA_SPEAR320_SOC_CONFIG_BASE + 0x0018)
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#define SPEAR320_UARTX_PCLK_MASK 0x1
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#define SPEAR320_UART2_PCLK_SHIFT 8
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#define SPEAR320_UART3_PCLK_SHIFT 9
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#define SPEAR320_UART4_PCLK_SHIFT 10
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#define SPEAR320_UART5_PCLK_SHIFT 11
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#define SPEAR320_UART6_PCLK_SHIFT 12
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#define SPEAR320_RS485_PCLK_SHIFT 13
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#endif /* __MACH_SPEAR3XX_H */
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