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9586a2ea68
The values of CPSR MODE mask are different between aarch32 and aarch64. It should use the right one according to the execution state. Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
307 lines
7.6 KiB
C
307 lines
7.6 KiB
C
/*
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* Copyright (C) 2012,2013 - ARM Ltd
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*
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* Derived from arch/arm/include/kvm_emulate.h
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* Copyright (C) 2012 - Virtual Open Systems and Columbia University
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* Author: Christoffer Dall <c.dall@virtualopensystems.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ARM64_KVM_EMULATE_H__
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#define __ARM64_KVM_EMULATE_H__
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#include <linux/kvm_host.h>
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#include <asm/esr.h>
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#include <asm/kvm_arm.h>
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#include <asm/kvm_mmio.h>
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#include <asm/ptrace.h>
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#include <asm/cputype.h>
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unsigned long *vcpu_reg32(const struct kvm_vcpu *vcpu, u8 reg_num);
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unsigned long *vcpu_spsr32(const struct kvm_vcpu *vcpu);
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bool kvm_condition_valid32(const struct kvm_vcpu *vcpu);
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void kvm_skip_instr32(struct kvm_vcpu *vcpu, bool is_wide_instr);
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void kvm_inject_undefined(struct kvm_vcpu *vcpu);
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void kvm_inject_dabt(struct kvm_vcpu *vcpu, unsigned long addr);
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void kvm_inject_pabt(struct kvm_vcpu *vcpu, unsigned long addr);
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static inline void vcpu_reset_hcr(struct kvm_vcpu *vcpu)
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{
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vcpu->arch.hcr_el2 = HCR_GUEST_FLAGS;
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if (test_bit(KVM_ARM_VCPU_EL1_32BIT, vcpu->arch.features))
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vcpu->arch.hcr_el2 &= ~HCR_RW;
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}
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static inline unsigned long vcpu_get_hcr(struct kvm_vcpu *vcpu)
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{
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return vcpu->arch.hcr_el2;
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}
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static inline void vcpu_set_hcr(struct kvm_vcpu *vcpu, unsigned long hcr)
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{
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vcpu->arch.hcr_el2 = hcr;
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}
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static inline unsigned long *vcpu_pc(const struct kvm_vcpu *vcpu)
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{
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return (unsigned long *)&vcpu_gp_regs(vcpu)->regs.pc;
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}
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static inline unsigned long *vcpu_elr_el1(const struct kvm_vcpu *vcpu)
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{
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return (unsigned long *)&vcpu_gp_regs(vcpu)->elr_el1;
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}
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static inline unsigned long *vcpu_cpsr(const struct kvm_vcpu *vcpu)
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{
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return (unsigned long *)&vcpu_gp_regs(vcpu)->regs.pstate;
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}
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static inline bool vcpu_mode_is_32bit(const struct kvm_vcpu *vcpu)
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{
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return !!(*vcpu_cpsr(vcpu) & PSR_MODE32_BIT);
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}
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static inline bool kvm_condition_valid(const struct kvm_vcpu *vcpu)
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{
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if (vcpu_mode_is_32bit(vcpu))
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return kvm_condition_valid32(vcpu);
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return true;
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}
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static inline void kvm_skip_instr(struct kvm_vcpu *vcpu, bool is_wide_instr)
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{
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if (vcpu_mode_is_32bit(vcpu))
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kvm_skip_instr32(vcpu, is_wide_instr);
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else
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*vcpu_pc(vcpu) += 4;
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}
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static inline void vcpu_set_thumb(struct kvm_vcpu *vcpu)
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{
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*vcpu_cpsr(vcpu) |= COMPAT_PSR_T_BIT;
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}
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/*
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* vcpu_get_reg and vcpu_set_reg should always be passed a register number
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* coming from a read of ESR_EL2. Otherwise, it may give the wrong result on
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* AArch32 with banked registers.
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*/
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static inline unsigned long vcpu_get_reg(const struct kvm_vcpu *vcpu,
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u8 reg_num)
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{
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return (reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs.regs[reg_num];
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}
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static inline void vcpu_set_reg(struct kvm_vcpu *vcpu, u8 reg_num,
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unsigned long val)
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{
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if (reg_num != 31)
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vcpu_gp_regs(vcpu)->regs.regs[reg_num] = val;
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}
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/* Get vcpu SPSR for current mode */
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static inline unsigned long *vcpu_spsr(const struct kvm_vcpu *vcpu)
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{
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if (vcpu_mode_is_32bit(vcpu))
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return vcpu_spsr32(vcpu);
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return (unsigned long *)&vcpu_gp_regs(vcpu)->spsr[KVM_SPSR_EL1];
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}
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static inline bool vcpu_mode_priv(const struct kvm_vcpu *vcpu)
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{
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u32 mode;
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if (vcpu_mode_is_32bit(vcpu)) {
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mode = *vcpu_cpsr(vcpu) & COMPAT_PSR_MODE_MASK;
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return mode > COMPAT_PSR_MODE_USR;
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}
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mode = *vcpu_cpsr(vcpu) & PSR_MODE_MASK;
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return mode != PSR_MODE_EL0t;
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}
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static inline u32 kvm_vcpu_get_hsr(const struct kvm_vcpu *vcpu)
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{
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return vcpu->arch.fault.esr_el2;
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}
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static inline unsigned long kvm_vcpu_get_hfar(const struct kvm_vcpu *vcpu)
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{
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return vcpu->arch.fault.far_el2;
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}
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static inline phys_addr_t kvm_vcpu_get_fault_ipa(const struct kvm_vcpu *vcpu)
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{
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return ((phys_addr_t)vcpu->arch.fault.hpfar_el2 & HPFAR_MASK) << 8;
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}
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static inline u32 kvm_vcpu_hvc_get_imm(const struct kvm_vcpu *vcpu)
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{
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return kvm_vcpu_get_hsr(vcpu) & ESR_ELx_xVC_IMM_MASK;
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}
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static inline bool kvm_vcpu_dabt_isvalid(const struct kvm_vcpu *vcpu)
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{
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return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_ISV);
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}
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static inline bool kvm_vcpu_dabt_iswrite(const struct kvm_vcpu *vcpu)
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{
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return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_WNR);
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}
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static inline bool kvm_vcpu_dabt_issext(const struct kvm_vcpu *vcpu)
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{
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return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_SSE);
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}
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static inline int kvm_vcpu_dabt_get_rd(const struct kvm_vcpu *vcpu)
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{
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return (kvm_vcpu_get_hsr(vcpu) & ESR_ELx_SRT_MASK) >> ESR_ELx_SRT_SHIFT;
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}
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static inline bool kvm_vcpu_dabt_isextabt(const struct kvm_vcpu *vcpu)
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{
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return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_EA);
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}
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static inline bool kvm_vcpu_dabt_iss1tw(const struct kvm_vcpu *vcpu)
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{
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return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_S1PTW);
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}
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static inline int kvm_vcpu_dabt_get_as(const struct kvm_vcpu *vcpu)
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{
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return 1 << ((kvm_vcpu_get_hsr(vcpu) & ESR_ELx_SAS) >> ESR_ELx_SAS_SHIFT);
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}
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/* This one is not specific to Data Abort */
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static inline bool kvm_vcpu_trap_il_is32bit(const struct kvm_vcpu *vcpu)
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{
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return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_IL);
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}
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static inline u8 kvm_vcpu_trap_get_class(const struct kvm_vcpu *vcpu)
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{
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return kvm_vcpu_get_hsr(vcpu) >> ESR_ELx_EC_SHIFT;
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}
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static inline bool kvm_vcpu_trap_is_iabt(const struct kvm_vcpu *vcpu)
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{
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return kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_IABT_LOW;
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}
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static inline u8 kvm_vcpu_trap_get_fault(const struct kvm_vcpu *vcpu)
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{
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return kvm_vcpu_get_hsr(vcpu) & ESR_ELx_FSC;
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}
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static inline u8 kvm_vcpu_trap_get_fault_type(const struct kvm_vcpu *vcpu)
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{
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return kvm_vcpu_get_hsr(vcpu) & ESR_ELx_FSC_TYPE;
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}
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static inline unsigned long kvm_vcpu_get_mpidr_aff(struct kvm_vcpu *vcpu)
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{
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return vcpu_sys_reg(vcpu, MPIDR_EL1) & MPIDR_HWID_BITMASK;
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}
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static inline void kvm_vcpu_set_be(struct kvm_vcpu *vcpu)
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{
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if (vcpu_mode_is_32bit(vcpu))
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*vcpu_cpsr(vcpu) |= COMPAT_PSR_E_BIT;
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else
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vcpu_sys_reg(vcpu, SCTLR_EL1) |= (1 << 25);
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}
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static inline bool kvm_vcpu_is_be(struct kvm_vcpu *vcpu)
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{
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if (vcpu_mode_is_32bit(vcpu))
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return !!(*vcpu_cpsr(vcpu) & COMPAT_PSR_E_BIT);
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return !!(vcpu_sys_reg(vcpu, SCTLR_EL1) & (1 << 25));
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}
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static inline unsigned long vcpu_data_guest_to_host(struct kvm_vcpu *vcpu,
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unsigned long data,
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unsigned int len)
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{
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if (kvm_vcpu_is_be(vcpu)) {
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switch (len) {
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case 1:
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return data & 0xff;
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case 2:
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return be16_to_cpu(data & 0xffff);
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case 4:
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return be32_to_cpu(data & 0xffffffff);
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default:
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return be64_to_cpu(data);
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}
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} else {
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switch (len) {
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case 1:
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return data & 0xff;
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case 2:
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return le16_to_cpu(data & 0xffff);
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case 4:
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return le32_to_cpu(data & 0xffffffff);
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default:
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return le64_to_cpu(data);
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}
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}
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return data; /* Leave LE untouched */
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}
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static inline unsigned long vcpu_data_host_to_guest(struct kvm_vcpu *vcpu,
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unsigned long data,
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unsigned int len)
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{
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if (kvm_vcpu_is_be(vcpu)) {
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switch (len) {
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case 1:
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return data & 0xff;
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case 2:
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return cpu_to_be16(data & 0xffff);
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case 4:
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return cpu_to_be32(data & 0xffffffff);
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default:
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return cpu_to_be64(data);
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}
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} else {
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switch (len) {
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case 1:
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return data & 0xff;
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case 2:
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return cpu_to_le16(data & 0xffff);
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case 4:
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return cpu_to_le32(data & 0xffffffff);
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default:
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return cpu_to_le64(data);
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}
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}
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return data; /* Leave LE untouched */
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}
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#endif /* __ARM64_KVM_EMULATE_H__ */
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