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6ab3d5624e
Signed-off-by: Jörn Engel <joern@wohnheim.fh-wedel.de> Signed-off-by: Adrian Bunk <bunk@stusta.de>
631 lines
18 KiB
ArmAsm
631 lines
18 KiB
ArmAsm
/* tlb-miss.S: TLB miss handlers
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*
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* Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
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* Written by David Howells (dhowells@redhat.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/sys.h>
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#include <linux/linkage.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/highmem.h>
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#include <asm/spr-regs.h>
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.section .text
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.balign 4
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.globl __entry_insn_mmu_miss
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__entry_insn_mmu_miss:
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break
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nop
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.globl __entry_insn_mmu_exception
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__entry_insn_mmu_exception:
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break
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nop
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.globl __entry_data_mmu_miss
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__entry_data_mmu_miss:
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break
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nop
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.globl __entry_data_mmu_exception
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__entry_data_mmu_exception:
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break
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nop
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###############################################################################
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#
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# handle a lookup failure of one sort or another in a kernel TLB handler
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# On entry:
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# GR29 - faulting address
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# SCR2 - saved CCR
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#
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###############################################################################
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.type __tlb_kernel_fault,@function
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__tlb_kernel_fault:
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# see if we're supposed to re-enable single-step mode upon return
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sethi.p %hi(__break_tlb_miss_return_break),gr30
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setlo %lo(__break_tlb_miss_return_break),gr30
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movsg pcsr,gr31
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subcc gr31,gr30,gr0,icc0
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beq icc0,#0,__tlb_kernel_fault_sstep
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movsg scr2,gr30
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movgs gr30,ccr
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movgs gr29,scr2 /* save EAR0 value */
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sethi.p %hi(__kernel_current_task),gr29
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setlo %lo(__kernel_current_task),gr29
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ldi.p @(gr29,#0),gr29 /* restore GR29 */
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bra __entry_kernel_handle_mmu_fault
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# we've got to re-enable single-stepping
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__tlb_kernel_fault_sstep:
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sethi.p %hi(__break_tlb_miss_real_return_info),gr30
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setlo %lo(__break_tlb_miss_real_return_info),gr30
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lddi @(gr30,0),gr30
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movgs gr30,pcsr
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movgs gr31,psr
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movsg scr2,gr30
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movgs gr30,ccr
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movgs gr29,scr2 /* save EAR0 value */
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sethi.p %hi(__kernel_current_task),gr29
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setlo %lo(__kernel_current_task),gr29
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ldi.p @(gr29,#0),gr29 /* restore GR29 */
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bra __entry_kernel_handle_mmu_fault_sstep
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.size __tlb_kernel_fault, .-__tlb_kernel_fault
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###############################################################################
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#
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# handle a lookup failure of one sort or another in a user TLB handler
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# On entry:
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# GR28 - faulting address
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# SCR2 - saved CCR
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#
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###############################################################################
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.type __tlb_user_fault,@function
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__tlb_user_fault:
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# see if we're supposed to re-enable single-step mode upon return
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sethi.p %hi(__break_tlb_miss_return_break),gr30
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setlo %lo(__break_tlb_miss_return_break),gr30
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movsg pcsr,gr31
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subcc gr31,gr30,gr0,icc0
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beq icc0,#0,__tlb_user_fault_sstep
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movsg scr2,gr30
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movgs gr30,ccr
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bra __entry_uspace_handle_mmu_fault
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# we've got to re-enable single-stepping
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__tlb_user_fault_sstep:
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sethi.p %hi(__break_tlb_miss_real_return_info),gr30
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setlo %lo(__break_tlb_miss_real_return_info),gr30
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lddi @(gr30,0),gr30
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movgs gr30,pcsr
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movgs gr31,psr
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movsg scr2,gr30
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movgs gr30,ccr
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bra __entry_uspace_handle_mmu_fault_sstep
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.size __tlb_user_fault, .-__tlb_user_fault
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###############################################################################
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#
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# Kernel instruction TLB miss handler
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# On entry:
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# GR1 - kernel stack pointer
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# GR28 - saved exception frame pointer
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# GR29 - faulting address
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# GR31 - EAR0 ^ SCR0
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# SCR0 - base of virtual range covered by cached PGE from last ITLB miss (or 0xffffffff)
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# DAMR3 - mapped page directory
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# DAMR4 - mapped page table as matched by SCR0
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#
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###############################################################################
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.globl __entry_kernel_insn_tlb_miss
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.type __entry_kernel_insn_tlb_miss,@function
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__entry_kernel_insn_tlb_miss:
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#if 0
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sethi.p %hi(0xe1200004),gr30
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setlo %lo(0xe1200004),gr30
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st gr0,@(gr30,gr0)
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sethi.p %hi(0xffc00100),gr30
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setlo %lo(0xffc00100),gr30
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sth gr30,@(gr30,gr0)
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membar
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#endif
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movsg ccr,gr30 /* save CCR */
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movgs gr30,scr2
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# see if the cached page table mapping is appropriate
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srlicc.p gr31,#26,gr0,icc0
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setlos 0x3ffc,gr30
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srli.p gr29,#12,gr31 /* use EAR0[25:14] as PTE index */
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bne icc0,#0,__itlb_k_PTD_miss
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__itlb_k_PTD_mapped:
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# access the PTD with EAR0[25:14]
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# - DAMLR4 points to the virtual address of the appropriate page table
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# - the PTD holds 4096 PTEs
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# - the PTD must be accessed uncached
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# - the PTE must be marked accessed if it was valid
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#
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and gr31,gr30,gr31
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movsg damlr4,gr30
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add gr30,gr31,gr31
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ldi @(gr31,#0),gr30 /* fetch the PTE */
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andicc gr30,#_PAGE_PRESENT,gr0,icc0
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ori.p gr30,#_PAGE_ACCESSED,gr30
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beq icc0,#0,__tlb_kernel_fault /* jump if PTE invalid */
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sti.p gr30,@(gr31,#0) /* update the PTE */
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andi gr30,#~_PAGE_ACCESSED,gr30
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# we're using IAMR1 as an extra TLB entry
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# - punt the entry here (if valid) to the real TLB and then replace with the new PTE
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# - need to check DAMR1 lest we cause an multiple-DAT-hit exception
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# - IAMPR1 has no WP bit, and we mustn't lose WP information
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movsg iampr1,gr31
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andicc gr31,#xAMPRx_V,gr0,icc0
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setlos.p 0xfffff000,gr31
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beq icc0,#0,__itlb_k_nopunt /* punt not required */
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movsg iamlr1,gr31
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movgs gr31,tplr /* set TPLR.CXN */
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tlbpr gr31,gr0,#4,#0 /* delete matches from TLB, IAMR1, DAMR1 */
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movsg dampr1,gr31
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ori gr31,#xAMPRx_V,gr31 /* entry was invalidated by tlbpr #4 */
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movgs gr31,tppr
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movsg iamlr1,gr31 /* set TPLR.CXN */
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movgs gr31,tplr
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tlbpr gr31,gr0,#2,#0 /* save to the TLB */
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movsg tpxr,gr31 /* check the TLB write error flag */
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andicc.p gr31,#TPXR_E,gr0,icc0
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setlos #0xfffff000,gr31
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bne icc0,#0,__tlb_kernel_fault
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__itlb_k_nopunt:
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# assemble the new TLB entry
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and gr29,gr31,gr29
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movsg cxnr,gr31
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or gr29,gr31,gr29
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movgs gr29,iamlr1 /* xAMLR = address | context number */
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movgs gr30,iampr1
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movgs gr29,damlr1
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movgs gr30,dampr1
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# return, restoring registers
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movsg scr2,gr30
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movgs gr30,ccr
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sethi.p %hi(__kernel_current_task),gr29
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setlo %lo(__kernel_current_task),gr29
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ldi @(gr29,#0),gr29
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rett #0
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beq icc0,#3,0 /* prevent icache prefetch */
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# the PTE we want wasn't in the PTD we have mapped, so we need to go looking for a more
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# appropriate page table and map that instead
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# - access the PGD with EAR0[31:26]
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# - DAMLR3 points to the virtual address of the page directory
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# - the PGD holds 64 PGEs and each PGE/PME points to a set of page tables
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__itlb_k_PTD_miss:
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srli gr29,#26,gr31 /* calculate PGE offset */
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slli gr31,#8,gr31 /* and clear bottom bits */
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movsg damlr3,gr30
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ld @(gr31,gr30),gr30 /* access the PGE */
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andicc.p gr30,#_PAGE_PRESENT,gr0,icc0
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andicc gr30,#xAMPRx_SS,gr0,icc1
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# map this PTD instead and record coverage address
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ori.p gr30,#xAMPRx_L|xAMPRx_SS_16Kb|xAMPRx_S|xAMPRx_C|xAMPRx_V,gr30
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beq icc0,#0,__tlb_kernel_fault /* jump if PGE not present */
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slli.p gr31,#18,gr31
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bne icc1,#0,__itlb_k_bigpage
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movgs gr30,dampr4
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movgs gr31,scr0
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# we can now resume normal service
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setlos 0x3ffc,gr30
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srli.p gr29,#12,gr31 /* use EAR0[25:14] as PTE index */
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bra __itlb_k_PTD_mapped
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__itlb_k_bigpage:
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break
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nop
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.size __entry_kernel_insn_tlb_miss, .-__entry_kernel_insn_tlb_miss
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###############################################################################
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#
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# Kernel data TLB miss handler
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# On entry:
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# GR1 - kernel stack pointer
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# GR28 - saved exception frame pointer
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# GR29 - faulting address
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# GR31 - EAR0 ^ SCR1
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# SCR1 - base of virtual range covered by cached PGE from last DTLB miss (or 0xffffffff)
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# DAMR3 - mapped page directory
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# DAMR5 - mapped page table as matched by SCR1
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#
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###############################################################################
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.globl __entry_kernel_data_tlb_miss
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.type __entry_kernel_data_tlb_miss,@function
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__entry_kernel_data_tlb_miss:
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#if 0
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sethi.p %hi(0xe1200004),gr30
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setlo %lo(0xe1200004),gr30
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st gr0,@(gr30,gr0)
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sethi.p %hi(0xffc00100),gr30
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setlo %lo(0xffc00100),gr30
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sth gr30,@(gr30,gr0)
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membar
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#endif
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movsg ccr,gr30 /* save CCR */
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movgs gr30,scr2
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# see if the cached page table mapping is appropriate
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srlicc.p gr31,#26,gr0,icc0
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setlos 0x3ffc,gr30
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srli.p gr29,#12,gr31 /* use EAR0[25:14] as PTE index */
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bne icc0,#0,__dtlb_k_PTD_miss
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__dtlb_k_PTD_mapped:
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# access the PTD with EAR0[25:14]
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# - DAMLR5 points to the virtual address of the appropriate page table
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# - the PTD holds 4096 PTEs
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# - the PTD must be accessed uncached
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# - the PTE must be marked accessed if it was valid
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#
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and gr31,gr30,gr31
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movsg damlr5,gr30
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add gr30,gr31,gr31
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ldi @(gr31,#0),gr30 /* fetch the PTE */
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andicc gr30,#_PAGE_PRESENT,gr0,icc0
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ori.p gr30,#_PAGE_ACCESSED,gr30
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beq icc0,#0,__tlb_kernel_fault /* jump if PTE invalid */
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sti.p gr30,@(gr31,#0) /* update the PTE */
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andi gr30,#~_PAGE_ACCESSED,gr30
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# we're using DAMR1 as an extra TLB entry
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# - punt the entry here (if valid) to the real TLB and then replace with the new PTE
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# - need to check IAMR1 lest we cause an multiple-DAT-hit exception
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movsg dampr1,gr31
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andicc gr31,#xAMPRx_V,gr0,icc0
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setlos.p 0xfffff000,gr31
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beq icc0,#0,__dtlb_k_nopunt /* punt not required */
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movsg damlr1,gr31
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movgs gr31,tplr /* set TPLR.CXN */
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tlbpr gr31,gr0,#4,#0 /* delete matches from TLB, IAMR1, DAMR1 */
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movsg dampr1,gr31
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ori gr31,#xAMPRx_V,gr31 /* entry was invalidated by tlbpr #4 */
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movgs gr31,tppr
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movsg damlr1,gr31 /* set TPLR.CXN */
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movgs gr31,tplr
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tlbpr gr31,gr0,#2,#0 /* save to the TLB */
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movsg tpxr,gr31 /* check the TLB write error flag */
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andicc.p gr31,#TPXR_E,gr0,icc0
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setlos #0xfffff000,gr31
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bne icc0,#0,__tlb_kernel_fault
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__dtlb_k_nopunt:
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# assemble the new TLB entry
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and gr29,gr31,gr29
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movsg cxnr,gr31
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or gr29,gr31,gr29
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movgs gr29,iamlr1 /* xAMLR = address | context number */
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movgs gr30,iampr1
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movgs gr29,damlr1
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movgs gr30,dampr1
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# return, restoring registers
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movsg scr2,gr30
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movgs gr30,ccr
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sethi.p %hi(__kernel_current_task),gr29
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setlo %lo(__kernel_current_task),gr29
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ldi @(gr29,#0),gr29
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rett #0
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beq icc0,#3,0 /* prevent icache prefetch */
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# the PTE we want wasn't in the PTD we have mapped, so we need to go looking for a more
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# appropriate page table and map that instead
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# - access the PGD with EAR0[31:26]
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# - DAMLR3 points to the virtual address of the page directory
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# - the PGD holds 64 PGEs and each PGE/PME points to a set of page tables
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__dtlb_k_PTD_miss:
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srli gr29,#26,gr31 /* calculate PGE offset */
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slli gr31,#8,gr31 /* and clear bottom bits */
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movsg damlr3,gr30
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ld @(gr31,gr30),gr30 /* access the PGE */
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andicc.p gr30,#_PAGE_PRESENT,gr0,icc0
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andicc gr30,#xAMPRx_SS,gr0,icc1
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# map this PTD instead and record coverage address
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ori.p gr30,#xAMPRx_L|xAMPRx_SS_16Kb|xAMPRx_S|xAMPRx_C|xAMPRx_V,gr30
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beq icc0,#0,__tlb_kernel_fault /* jump if PGE not present */
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slli.p gr31,#18,gr31
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bne icc1,#0,__dtlb_k_bigpage
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movgs gr30,dampr5
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movgs gr31,scr1
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# we can now resume normal service
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setlos 0x3ffc,gr30
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srli.p gr29,#12,gr31 /* use EAR0[25:14] as PTE index */
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bra __dtlb_k_PTD_mapped
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__dtlb_k_bigpage:
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break
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nop
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.size __entry_kernel_data_tlb_miss, .-__entry_kernel_data_tlb_miss
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###############################################################################
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#
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# Userspace instruction TLB miss handler (with PGE prediction)
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# On entry:
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# GR28 - faulting address
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# GR31 - EAR0 ^ SCR0
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# SCR0 - base of virtual range covered by cached PGE from last ITLB miss (or 0xffffffff)
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# DAMR3 - mapped page directory
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# DAMR4 - mapped page table as matched by SCR0
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#
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###############################################################################
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.globl __entry_user_insn_tlb_miss
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.type __entry_user_insn_tlb_miss,@function
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__entry_user_insn_tlb_miss:
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#if 0
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sethi.p %hi(0xe1200004),gr30
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setlo %lo(0xe1200004),gr30
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st gr0,@(gr30,gr0)
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sethi.p %hi(0xffc00100),gr30
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setlo %lo(0xffc00100),gr30
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sth gr30,@(gr30,gr0)
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membar
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#endif
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movsg ccr,gr30 /* save CCR */
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movgs gr30,scr2
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# see if the cached page table mapping is appropriate
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srlicc.p gr31,#26,gr0,icc0
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setlos 0x3ffc,gr30
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srli.p gr28,#12,gr31 /* use EAR0[25:14] as PTE index */
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bne icc0,#0,__itlb_u_PTD_miss
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__itlb_u_PTD_mapped:
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# access the PTD with EAR0[25:14]
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# - DAMLR4 points to the virtual address of the appropriate page table
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# - the PTD holds 4096 PTEs
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# - the PTD must be accessed uncached
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# - the PTE must be marked accessed if it was valid
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#
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and gr31,gr30,gr31
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movsg damlr4,gr30
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add gr30,gr31,gr31
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ldi @(gr31,#0),gr30 /* fetch the PTE */
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andicc gr30,#_PAGE_PRESENT,gr0,icc0
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ori.p gr30,#_PAGE_ACCESSED,gr30
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beq icc0,#0,__tlb_user_fault /* jump if PTE invalid */
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sti.p gr30,@(gr31,#0) /* update the PTE */
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andi gr30,#~_PAGE_ACCESSED,gr30
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# we're using IAMR1/DAMR1 as an extra TLB entry
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# - punt the entry here (if valid) to the real TLB and then replace with the new PTE
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movsg dampr1,gr31
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andicc gr31,#xAMPRx_V,gr0,icc0
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setlos.p 0xfffff000,gr31
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beq icc0,#0,__itlb_u_nopunt /* punt not required */
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movsg dampr1,gr31
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movgs gr31,tppr
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movsg damlr1,gr31 /* set TPLR.CXN */
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movgs gr31,tplr
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tlbpr gr31,gr0,#2,#0 /* save to the TLB */
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movsg tpxr,gr31 /* check the TLB write error flag */
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andicc.p gr31,#TPXR_E,gr0,icc0
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setlos #0xfffff000,gr31
|
|
bne icc0,#0,__tlb_user_fault
|
|
|
|
__itlb_u_nopunt:
|
|
|
|
# assemble the new TLB entry
|
|
and gr28,gr31,gr28
|
|
movsg cxnr,gr31
|
|
or gr28,gr31,gr28
|
|
movgs gr28,iamlr1 /* xAMLR = address | context number */
|
|
movgs gr30,iampr1
|
|
movgs gr28,damlr1
|
|
movgs gr30,dampr1
|
|
|
|
# return, restoring registers
|
|
movsg scr2,gr30
|
|
movgs gr30,ccr
|
|
rett #0
|
|
beq icc0,#3,0 /* prevent icache prefetch */
|
|
|
|
# the PTE we want wasn't in the PTD we have mapped, so we need to go looking for a more
|
|
# appropriate page table and map that instead
|
|
# - access the PGD with EAR0[31:26]
|
|
# - DAMLR3 points to the virtual address of the page directory
|
|
# - the PGD holds 64 PGEs and each PGE/PME points to a set of page tables
|
|
__itlb_u_PTD_miss:
|
|
srli gr28,#26,gr31 /* calculate PGE offset */
|
|
slli gr31,#8,gr31 /* and clear bottom bits */
|
|
|
|
movsg damlr3,gr30
|
|
ld @(gr31,gr30),gr30 /* access the PGE */
|
|
|
|
andicc.p gr30,#_PAGE_PRESENT,gr0,icc0
|
|
andicc gr30,#xAMPRx_SS,gr0,icc1
|
|
|
|
# map this PTD instead and record coverage address
|
|
ori.p gr30,#xAMPRx_L|xAMPRx_SS_16Kb|xAMPRx_S|xAMPRx_C|xAMPRx_V,gr30
|
|
beq icc0,#0,__tlb_user_fault /* jump if PGE not present */
|
|
slli.p gr31,#18,gr31
|
|
bne icc1,#0,__itlb_u_bigpage
|
|
movgs gr30,dampr4
|
|
movgs gr31,scr0
|
|
|
|
# we can now resume normal service
|
|
setlos 0x3ffc,gr30
|
|
srli.p gr28,#12,gr31 /* use EAR0[25:14] as PTE index */
|
|
bra __itlb_u_PTD_mapped
|
|
|
|
__itlb_u_bigpage:
|
|
break
|
|
nop
|
|
|
|
.size __entry_user_insn_tlb_miss, .-__entry_user_insn_tlb_miss
|
|
|
|
###############################################################################
|
|
#
|
|
# Userspace data TLB miss handler
|
|
# On entry:
|
|
# GR28 - faulting address
|
|
# GR31 - EAR0 ^ SCR1
|
|
# SCR1 - base of virtual range covered by cached PGE from last DTLB miss (or 0xffffffff)
|
|
# DAMR3 - mapped page directory
|
|
# DAMR5 - mapped page table as matched by SCR1
|
|
#
|
|
###############################################################################
|
|
.globl __entry_user_data_tlb_miss
|
|
.type __entry_user_data_tlb_miss,@function
|
|
__entry_user_data_tlb_miss:
|
|
#if 0
|
|
sethi.p %hi(0xe1200004),gr30
|
|
setlo %lo(0xe1200004),gr30
|
|
st gr0,@(gr30,gr0)
|
|
sethi.p %hi(0xffc00100),gr30
|
|
setlo %lo(0xffc00100),gr30
|
|
sth gr30,@(gr30,gr0)
|
|
membar
|
|
#endif
|
|
|
|
movsg ccr,gr30 /* save CCR */
|
|
movgs gr30,scr2
|
|
|
|
# see if the cached page table mapping is appropriate
|
|
srlicc.p gr31,#26,gr0,icc0
|
|
setlos 0x3ffc,gr30
|
|
srli.p gr28,#12,gr31 /* use EAR0[25:14] as PTE index */
|
|
bne icc0,#0,__dtlb_u_PTD_miss
|
|
|
|
__dtlb_u_PTD_mapped:
|
|
# access the PTD with EAR0[25:14]
|
|
# - DAMLR5 points to the virtual address of the appropriate page table
|
|
# - the PTD holds 4096 PTEs
|
|
# - the PTD must be accessed uncached
|
|
# - the PTE must be marked accessed if it was valid
|
|
#
|
|
and gr31,gr30,gr31
|
|
movsg damlr5,gr30
|
|
|
|
__dtlb_u_using_iPTD:
|
|
add gr30,gr31,gr31
|
|
ldi @(gr31,#0),gr30 /* fetch the PTE */
|
|
andicc gr30,#_PAGE_PRESENT,gr0,icc0
|
|
ori.p gr30,#_PAGE_ACCESSED,gr30
|
|
beq icc0,#0,__tlb_user_fault /* jump if PTE invalid */
|
|
sti.p gr30,@(gr31,#0) /* update the PTE */
|
|
andi gr30,#~_PAGE_ACCESSED,gr30
|
|
|
|
# we're using DAMR1 as an extra TLB entry
|
|
# - punt the entry here (if valid) to the real TLB and then replace with the new PTE
|
|
movsg dampr1,gr31
|
|
andicc gr31,#xAMPRx_V,gr0,icc0
|
|
setlos.p 0xfffff000,gr31
|
|
beq icc0,#0,__dtlb_u_nopunt /* punt not required */
|
|
|
|
movsg dampr1,gr31
|
|
movgs gr31,tppr
|
|
movsg damlr1,gr31 /* set TPLR.CXN */
|
|
movgs gr31,tplr
|
|
tlbpr gr31,gr0,#2,#0 /* save to the TLB */
|
|
movsg tpxr,gr31 /* check the TLB write error flag */
|
|
andicc.p gr31,#TPXR_E,gr0,icc0
|
|
setlos #0xfffff000,gr31
|
|
bne icc0,#0,__tlb_user_fault
|
|
|
|
__dtlb_u_nopunt:
|
|
|
|
# assemble the new TLB entry
|
|
and gr28,gr31,gr28
|
|
movsg cxnr,gr31
|
|
or gr28,gr31,gr28
|
|
movgs gr28,iamlr1 /* xAMLR = address | context number */
|
|
movgs gr30,iampr1
|
|
movgs gr28,damlr1
|
|
movgs gr30,dampr1
|
|
|
|
# return, restoring registers
|
|
movsg scr2,gr30
|
|
movgs gr30,ccr
|
|
rett #0
|
|
beq icc0,#3,0 /* prevent icache prefetch */
|
|
|
|
# the PTE we want wasn't in the PTD we have mapped, so we need to go looking for a more
|
|
# appropriate page table and map that instead
|
|
# - first of all, check the insn PGE cache - we may well get a hit there
|
|
# - access the PGD with EAR0[31:26]
|
|
# - DAMLR3 points to the virtual address of the page directory
|
|
# - the PGD holds 64 PGEs and each PGE/PME points to a set of page tables
|
|
__dtlb_u_PTD_miss:
|
|
movsg scr0,gr31 /* consult the insn-PGE-cache key */
|
|
xor gr28,gr31,gr31
|
|
srlicc gr31,#26,gr0,icc0
|
|
srli gr28,#12,gr31 /* use EAR0[25:14] as PTE index */
|
|
bne icc0,#0,__dtlb_u_iPGE_miss
|
|
|
|
# what we're looking for is covered by the insn-PGE-cache
|
|
setlos 0x3ffc,gr30
|
|
and gr31,gr30,gr31
|
|
movsg damlr4,gr30
|
|
bra __dtlb_u_using_iPTD
|
|
|
|
__dtlb_u_iPGE_miss:
|
|
srli gr28,#26,gr31 /* calculate PGE offset */
|
|
slli gr31,#8,gr31 /* and clear bottom bits */
|
|
|
|
movsg damlr3,gr30
|
|
ld @(gr31,gr30),gr30 /* access the PGE */
|
|
|
|
andicc.p gr30,#_PAGE_PRESENT,gr0,icc0
|
|
andicc gr30,#xAMPRx_SS,gr0,icc1
|
|
|
|
# map this PTD instead and record coverage address
|
|
ori.p gr30,#xAMPRx_L|xAMPRx_SS_16Kb|xAMPRx_S|xAMPRx_C|xAMPRx_V,gr30
|
|
beq icc0,#0,__tlb_user_fault /* jump if PGE not present */
|
|
slli.p gr31,#18,gr31
|
|
bne icc1,#0,__dtlb_u_bigpage
|
|
movgs gr30,dampr5
|
|
movgs gr31,scr1
|
|
|
|
# we can now resume normal service
|
|
setlos 0x3ffc,gr30
|
|
srli.p gr28,#12,gr31 /* use EAR0[25:14] as PTE index */
|
|
bra __dtlb_u_PTD_mapped
|
|
|
|
__dtlb_u_bigpage:
|
|
break
|
|
nop
|
|
|
|
.size __entry_user_data_tlb_miss, .-__entry_user_data_tlb_miss
|