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8bd26e3a7e
The __cpuinit type of throwaway sections might have made sense
some time ago when RAM was more constrained, but now the savings
do not offset the cost and complications. For example, the fix in
commit 5e427ec2d0 ("x86: Fix bit corruption at CPU resume time")
is a good example of the nasty type of bugs that can be created
with improper use of the various __init prefixes.
After a discussion on LKML[1] it was decided that cpuinit should go
the way of devinit and be phased out. Once all the users are gone,
we can then finally remove the macros themselves from linux/init.h.
Note that some harmless section mismatch warnings may result, since
notify_cpu_starting() and cpu_up() are arch independent (kernel/cpu.c)
and are flagged as __cpuinit -- so if we remove the __cpuinit from
the arch specific callers, we will also get section mismatch warnings.
As an intermediate step, we intend to turn the linux/init.h cpuinit
related content into no-ops as early as possible, since that will get
rid of these warnings. In any case, they are temporary and harmless.
This removes all the ARM uses of the __cpuinit macros from C code,
and all __CPUINIT from assembly code. It also had two ".previous"
section statements that were paired off against __CPUINIT
(aka .section ".cpuinit.text") that also get removed here.
[1] https://lkml.org/lkml/2013/5/20/589
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Will Deacon <will.deacon@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
241 lines
6.5 KiB
C
241 lines
6.5 KiB
C
/*
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* OMAP4 SMP source file. It contains platform specific fucntions
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* needed for the linux smp kernel.
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*
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* Copyright (C) 2009 Texas Instruments, Inc.
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*
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* Author:
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* Santosh Shilimkar <santosh.shilimkar@ti.com>
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*
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* Platform file needed for the OMAP4 SMP. This file is based on arm
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* realview smp platform.
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* * Copyright (c) 2002 ARM Limited.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/device.h>
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#include <linux/smp.h>
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#include <linux/io.h>
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#include <linux/irqchip/arm-gic.h>
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#include <asm/smp_scu.h>
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#include "omap-secure.h"
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#include "omap-wakeupgen.h"
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#include <asm/cputype.h>
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#include "soc.h"
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#include "iomap.h"
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#include "common.h"
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#include "clockdomain.h"
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#include "pm.h"
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#define CPU_MASK 0xff0ffff0
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#define CPU_CORTEX_A9 0x410FC090
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#define CPU_CORTEX_A15 0x410FC0F0
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#define OMAP5_CORE_COUNT 0x2
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u16 pm44xx_errata;
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/* SCU base address */
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static void __iomem *scu_base;
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static DEFINE_SPINLOCK(boot_lock);
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void __iomem *omap4_get_scu_base(void)
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{
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return scu_base;
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}
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static void omap4_secondary_init(unsigned int cpu)
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{
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/*
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* Configure ACTRL and enable NS SMP bit access on CPU1 on HS device.
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* OMAP44XX EMU/HS devices - CPU0 SMP bit access is enabled in PPA
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* init and for CPU1, a secure PPA API provided. CPU0 must be ON
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* while executing NS_SMP API on CPU1 and PPA version must be 1.4.0+.
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* OMAP443X GP devices- SMP bit isn't accessible.
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* OMAP446X GP devices - SMP bit access is enabled on both CPUs.
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*/
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if (cpu_is_omap443x() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
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omap_secure_dispatcher(OMAP4_PPA_CPU_ACTRL_SMP_INDEX,
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4, 0, 0, 0, 0, 0);
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/*
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* Synchronise with the boot thread.
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*/
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spin_lock(&boot_lock);
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spin_unlock(&boot_lock);
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}
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static int omap4_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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static struct clockdomain *cpu1_clkdm;
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static bool booted;
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static struct powerdomain *cpu1_pwrdm;
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void __iomem *base = omap_get_wakeupgen_base();
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/*
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* Set synchronisation state between this boot processor
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* and the secondary one
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*/
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spin_lock(&boot_lock);
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/*
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* Update the AuxCoreBoot0 with boot state for secondary core.
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* omap4_secondary_startup() routine will hold the secondary core till
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* the AuxCoreBoot1 register is updated with cpu state
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* A barrier is added to ensure that write buffer is drained
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*/
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if (omap_secure_apis_support())
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omap_modify_auxcoreboot0(0x200, 0xfffffdff);
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else
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__raw_writel(0x20, base + OMAP_AUX_CORE_BOOT_0);
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if (!cpu1_clkdm && !cpu1_pwrdm) {
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cpu1_clkdm = clkdm_lookup("mpu1_clkdm");
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cpu1_pwrdm = pwrdm_lookup("cpu1_pwrdm");
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}
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/*
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* The SGI(Software Generated Interrupts) are not wakeup capable
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* from low power states. This is known limitation on OMAP4 and
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* needs to be worked around by using software forced clockdomain
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* wake-up. To wakeup CPU1, CPU0 forces the CPU1 clockdomain to
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* software force wakeup. The clockdomain is then put back to
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* hardware supervised mode.
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* More details can be found in OMAP4430 TRM - Version J
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* Section :
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* 4.3.4.2 Power States of CPU0 and CPU1
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*/
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if (booted && cpu1_pwrdm && cpu1_clkdm) {
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/*
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* GIC distributor control register has changed between
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* CortexA9 r1pX and r2pX. The Control Register secure
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* banked version is now composed of 2 bits:
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* bit 0 == Secure Enable
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* bit 1 == Non-Secure Enable
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* The Non-Secure banked register has not changed
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* Because the ROM Code is based on the r1pX GIC, the CPU1
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* GIC restoration will cause a problem to CPU0 Non-Secure SW.
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* The workaround must be:
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* 1) Before doing the CPU1 wakeup, CPU0 must disable
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* the GIC distributor
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* 2) CPU1 must re-enable the GIC distributor on
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* it's wakeup path.
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*/
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if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD)) {
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local_irq_disable();
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gic_dist_disable();
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}
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/*
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* Ensure that CPU power state is set to ON to avoid CPU
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* powerdomain transition on wfi
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*/
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clkdm_wakeup(cpu1_clkdm);
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omap_set_pwrdm_state(cpu1_pwrdm, PWRDM_POWER_ON);
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clkdm_allow_idle(cpu1_clkdm);
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if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD)) {
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while (gic_dist_disabled()) {
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udelay(1);
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cpu_relax();
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}
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gic_timer_retrigger();
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local_irq_enable();
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}
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} else {
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dsb_sev();
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booted = true;
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}
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arch_send_wakeup_ipi_mask(cpumask_of(cpu));
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/*
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* Now the secondary core is starting up let it run its
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* calibrations, then wait for it to finish
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*/
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spin_unlock(&boot_lock);
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return 0;
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}
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/*
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* Initialise the CPU possible map early - this describes the CPUs
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* which may be present or become present in the system.
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*/
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static void __init omap4_smp_init_cpus(void)
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{
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unsigned int i = 0, ncores = 1, cpu_id;
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/* Use ARM cpuid check here, as SoC detection will not work so early */
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cpu_id = read_cpuid_id() & CPU_MASK;
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if (cpu_id == CPU_CORTEX_A9) {
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/*
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* Currently we can't call ioremap here because
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* SoC detection won't work until after init_early.
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*/
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scu_base = OMAP2_L4_IO_ADDRESS(scu_a9_get_base());
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BUG_ON(!scu_base);
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ncores = scu_get_core_count(scu_base);
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} else if (cpu_id == CPU_CORTEX_A15) {
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ncores = OMAP5_CORE_COUNT;
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}
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/* sanity check */
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if (ncores > nr_cpu_ids) {
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pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
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ncores, nr_cpu_ids);
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ncores = nr_cpu_ids;
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}
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for (i = 0; i < ncores; i++)
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set_cpu_possible(i, true);
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}
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static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
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{
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void *startup_addr = omap4_secondary_startup;
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void __iomem *base = omap_get_wakeupgen_base();
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/*
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* Initialise the SCU and wake up the secondary core using
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* wakeup_secondary().
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*/
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if (scu_base)
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scu_enable(scu_base);
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if (cpu_is_omap446x()) {
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startup_addr = omap4460_secondary_startup;
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pm44xx_errata |= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD;
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}
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/*
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* Write the address of secondary startup routine into the
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* AuxCoreBoot1 where ROM code will jump and start executing
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* on secondary core once out of WFE
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* A barrier is added to ensure that write buffer is drained
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*/
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if (omap_secure_apis_support())
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omap_auxcoreboot_addr(virt_to_phys(startup_addr));
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else
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__raw_writel(virt_to_phys(omap5_secondary_startup),
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base + OMAP_AUX_CORE_BOOT_1);
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}
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struct smp_operations omap4_smp_ops __initdata = {
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.smp_init_cpus = omap4_smp_init_cpus,
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.smp_prepare_cpus = omap4_smp_prepare_cpus,
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.smp_secondary_init = omap4_secondary_init,
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.smp_boot_secondary = omap4_boot_secondary,
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#ifdef CONFIG_HOTPLUG_CPU
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.cpu_die = omap4_cpu_die,
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#endif
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};
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