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ded9477984
For LPAE, we have the following means for encoding writable or dirty
ptes:
L_PTE_DIRTY L_PTE_RDONLY
!pte_dirty && !pte_write 0 1
!pte_dirty && pte_write 0 1
pte_dirty && !pte_write 1 1
pte_dirty && pte_write 1 0
So we can't distinguish between writeable clean ptes and read only
ptes. This can cause problems with ptes being incorrectly flagged as
read only when they are writeable but not dirty.
This patch renumbers L_PTE_RDONLY from AP[2] to a software bit #58,
and adds additional logic to set AP[2] whenever the pte is read only
or not dirty. That way we can distinguish between clean writeable ptes
and read only ptes.
HugeTLB pages will use this new logic automatically.
We need to add some logic to Transparent HugePages to ensure that they
correctly interpret the revised pgprot permissions (L_PTE_RDONLY has
moved and no longer matches PMD_SECT_AP2). In the process of revising
THP, the names of the PMD software bits have been prefixed with L_ to
make them easier to distinguish from their hardware bit counterparts.
Signed-off-by: Steve Capper <steve.capper@linaro.org>
Reviewed-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
168 lines
4.7 KiB
ArmAsm
168 lines
4.7 KiB
ArmAsm
/*
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* arch/arm/mm/proc-v7-3level.S
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*
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* Copyright (C) 2001 Deep Blue Solutions Ltd.
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* Copyright (C) 2011 ARM Ltd.
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* Author: Catalin Marinas <catalin.marinas@arm.com>
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* based on arch/arm/mm/proc-v7-2level.S
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <asm/assembler.h>
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#define TTB_IRGN_NC (0 << 8)
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#define TTB_IRGN_WBWA (1 << 8)
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#define TTB_IRGN_WT (2 << 8)
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#define TTB_IRGN_WB (3 << 8)
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#define TTB_RGN_NC (0 << 10)
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#define TTB_RGN_OC_WBWA (1 << 10)
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#define TTB_RGN_OC_WT (2 << 10)
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#define TTB_RGN_OC_WB (3 << 10)
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#define TTB_S (3 << 12)
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#define TTB_EAE (1 << 31)
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/* PTWs cacheable, inner WB not shareable, outer WB not shareable */
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#define TTB_FLAGS_UP (TTB_IRGN_WB|TTB_RGN_OC_WB)
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#define PMD_FLAGS_UP (PMD_SECT_WB)
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/* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
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#define TTB_FLAGS_SMP (TTB_IRGN_WBWA|TTB_S|TTB_RGN_OC_WBWA)
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#define PMD_FLAGS_SMP (PMD_SECT_WBWA|PMD_SECT_S)
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#ifndef __ARMEB__
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# define rpgdl r0
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# define rpgdh r1
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#else
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# define rpgdl r1
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# define rpgdh r0
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#endif
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/*
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* cpu_v7_switch_mm(pgd_phys, tsk)
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*
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* Set the translation table base pointer to be pgd_phys (physical address of
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* the new TTB).
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*/
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ENTRY(cpu_v7_switch_mm)
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#ifdef CONFIG_MMU
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mmid r2, r2
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asid r2, r2
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orr rpgdh, rpgdh, r2, lsl #(48 - 32) @ upper 32-bits of pgd
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mcrr p15, 0, rpgdl, rpgdh, c2 @ set TTB 0
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isb
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#endif
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ret lr
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ENDPROC(cpu_v7_switch_mm)
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#ifdef __ARMEB__
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#define rl r3
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#define rh r2
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#else
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#define rl r2
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#define rh r3
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#endif
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/*
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* cpu_v7_set_pte_ext(ptep, pte)
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*
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* Set a level 2 translation table entry.
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* - ptep - pointer to level 3 translation table entry
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* - pte - PTE value to store (64-bit in r2 and r3)
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*/
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ENTRY(cpu_v7_set_pte_ext)
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#ifdef CONFIG_MMU
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tst rl, #L_PTE_VALID
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beq 1f
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tst rh, #1 << (57 - 32) @ L_PTE_NONE
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bicne rl, #L_PTE_VALID
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bne 1f
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eor ip, rh, #1 << (55 - 32) @ toggle L_PTE_DIRTY in temp reg to
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@ test for !L_PTE_DIRTY || L_PTE_RDONLY
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tst ip, #1 << (55 - 32) | 1 << (58 - 32)
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orrne rl, #PTE_AP2
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biceq rl, #PTE_AP2
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1: strd r2, r3, [r0]
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ALT_SMP(W(nop))
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ALT_UP (mcr p15, 0, r0, c7, c10, 1) @ flush_pte
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#endif
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ret lr
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ENDPROC(cpu_v7_set_pte_ext)
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/*
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* Memory region attributes for LPAE (defined in pgtable-3level.h):
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*
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* n = AttrIndx[2:0]
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*
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* n MAIR
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* UNCACHED 000 00000000
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* BUFFERABLE 001 01000100
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* DEV_WC 001 01000100
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* WRITETHROUGH 010 10101010
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* WRITEBACK 011 11101110
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* DEV_CACHED 011 11101110
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* DEV_SHARED 100 00000100
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* DEV_NONSHARED 100 00000100
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* unused 101
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* unused 110
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* WRITEALLOC 111 11111111
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*/
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.equ PRRR, 0xeeaa4400 @ MAIR0
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.equ NMRR, 0xff000004 @ MAIR1
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/*
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* Macro for setting up the TTBRx and TTBCR registers.
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* - \ttbr1 updated.
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*/
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.macro v7_ttb_setup, zero, ttbr0, ttbr1, tmp
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ldr \tmp, =swapper_pg_dir @ swapper_pg_dir virtual address
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mov \tmp, \tmp, lsr #ARCH_PGD_SHIFT
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cmp \ttbr1, \tmp @ PHYS_OFFSET > PAGE_OFFSET?
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mrc p15, 0, \tmp, c2, c0, 2 @ TTB control register
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orr \tmp, \tmp, #TTB_EAE
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ALT_SMP(orr \tmp, \tmp, #TTB_FLAGS_SMP)
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ALT_UP(orr \tmp, \tmp, #TTB_FLAGS_UP)
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ALT_SMP(orr \tmp, \tmp, #TTB_FLAGS_SMP << 16)
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ALT_UP(orr \tmp, \tmp, #TTB_FLAGS_UP << 16)
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/*
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* Only use split TTBRs if PHYS_OFFSET <= PAGE_OFFSET (cmp above),
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* otherwise booting secondary CPUs would end up using TTBR1 for the
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* identity mapping set up in TTBR0.
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*/
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orrls \tmp, \tmp, #TTBR1_SIZE @ TTBCR.T1SZ
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mcr p15, 0, \tmp, c2, c0, 2 @ TTBCR
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mov \tmp, \ttbr1, lsr #(32 - ARCH_PGD_SHIFT) @ upper bits
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mov \ttbr1, \ttbr1, lsl #ARCH_PGD_SHIFT @ lower bits
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addls \ttbr1, \ttbr1, #TTBR1_OFFSET
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mcrr p15, 1, \ttbr1, \zero, c2 @ load TTBR1
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mov \tmp, \ttbr0, lsr #(32 - ARCH_PGD_SHIFT) @ upper bits
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mov \ttbr0, \ttbr0, lsl #ARCH_PGD_SHIFT @ lower bits
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mcrr p15, 0, \ttbr0, \zero, c2 @ load TTBR0
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mcrr p15, 1, \ttbr1, \zero, c2 @ load TTBR1
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mcrr p15, 0, \ttbr0, \zero, c2 @ load TTBR0
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.endm
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/*
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* AT
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* TFR EV X F IHD LR S
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* .EEE ..EE PUI. .TAT 4RVI ZWRS BLDP WCAM
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* rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced
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* 11 0 110 1 0011 1100 .111 1101 < we want
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*/
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.align 2
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.type v7_crval, #object
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v7_crval:
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crval clear=0x0120c302, mmuset=0x30c23c7d, ucset=0x00c01c7c
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