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6e8b66c1b7
Fix a typo in "Peripherals". Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
89 lines
3.1 KiB
Plaintext
89 lines
3.1 KiB
Plaintext
* Freescale i.MX7 Dual IOMUX Controller
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iMX7D supports two iomuxc controllers, fsl,imx7d-iomuxc controller is similar
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as previous iMX SoC generation and fsl,imx7d-iomuxc-lpsr which provides low
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power state retention capabilities on gpios that are part of iomuxc-lpsr
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(GPIO1_IO7..GPIO1_IO0). While iomuxc-lpsr provides its own set of registers for
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mux and pad control settings, it shares the input select register from main
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iomuxc controller for daisy chain settings, the fsl,input-sel property extends
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fsl,imx-pinctrl driver to support iomuxc-lpsr controller.
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iomuxc_lpsr: iomuxc-lpsr@302c0000 {
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compatible = "fsl,imx7d-iomuxc-lpsr";
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reg = <0x302c0000 0x10000>;
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fsl,input-sel = <&iomuxc>;
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};
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iomuxc: iomuxc@30330000 {
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compatible = "fsl,imx7d-iomuxc";
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reg = <0x30330000 0x10000>;
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};
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Peripherals using pads from iomuxc-lpsr support low state retention power
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state, under LPSR mode GPIO's state of pads are retain.
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Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
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and usage.
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Required properties:
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- compatible: "fsl,imx7d-iomuxc" for main IOMUXC controller, or
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"fsl,imx7d-iomuxc-lpsr" for Low Power State Retention IOMUXC controller.
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- fsl,pins: each entry consists of 6 integers and represents the mux and config
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setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
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input_val> are specified using a PIN_FUNC_ID macro, which can be found in
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imx7d-pinfunc.h under device tree source folder. The last integer CONFIG is
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the pad setting value like pull-up on this pin. Please refer to i.MX7 Dual
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Reference Manual for detailed CONFIG settings.
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- fsl,input-sel: required property for iomuxc-lpsr controller, this property is
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a phandle for main iomuxc controller which shares the input select register for
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daisy chain settings.
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CONFIG bits definition:
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PAD_CTL_PUS_100K_DOWN (0 << 5)
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PAD_CTL_PUS_5K_UP (1 << 5)
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PAD_CTL_PUS_47K_UP (2 << 5)
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PAD_CTL_PUS_100K_UP (3 << 5)
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PAD_CTL_PUE (1 << 4)
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PAD_CTL_HYS (1 << 3)
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PAD_CTL_SRE_SLOW (1 << 2)
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PAD_CTL_SRE_FAST (0 << 2)
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PAD_CTL_DSE_X1 (0 << 0)
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PAD_CTL_DSE_X2 (1 << 0)
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PAD_CTL_DSE_X3 (2 << 0)
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PAD_CTL_DSE_X4 (3 << 0)
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Examples:
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While iomuxc-lpsr is intended to be used by dedicated peripherals to take
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advantages of LPSR power mode, is also possible that an IP to use pads from
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any of the iomux controllers. For example the I2C1 IP can use SCL pad from
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iomuxc-lpsr controller and SDA pad from iomuxc controller as:
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i2c1: i2c@30a20000 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1_1 &pinctrl_i2c1_2>;
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status = "okay";
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};
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iomuxc-lpsr@302c0000 {
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compatible = "fsl,imx7d-iomuxc-lpsr";
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reg = <0x302c0000 0x10000>;
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fsl,input-sel = <&iomuxc>;
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pinctrl_i2c1_1: i2c1grp-1 {
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fsl,pins = <
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MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x4000007f
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>;
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};
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};
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iomuxc@30330000 {
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compatible = "fsl,imx7d-iomuxc";
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reg = <0x30330000 0x10000>;
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pinctrl_i2c1_2: i2c1grp-2 {
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fsl,pins = <
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MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f
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>;
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};
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};
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