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ab5b0107cc
This change adds a new eDP connector in msm drm driver. With this
change, eDP panel can work with msm platform under drm framework.
v1: Initial change
v2: Address Rob's comments
Use generated header file for register definitions
Change to devm_* APIs
v3: Address Thierry's comments and rebase on top of atomic changes
Remove edp_bridge_mode_fixup
Remove backlight control code and rely on pwm-backlight
Remove continuous splash screen support for now
Change to gpiod_* APIs
v4: Fix kbuild test issue
Signed-off-by: Hai Li <hali@codeaurora.org>
[robclark: v5: rebase on drm_bridge changes in drm-next]
Signed-off-by: Rob Clark <robdclark@gmail.com>
107 lines
2.5 KiB
C
107 lines
2.5 KiB
C
/*
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* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include "edp.h"
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#include "edp.xml.h"
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#define EDP_MAX_LANE 4
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struct edp_phy {
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void __iomem *base;
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};
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bool msm_edp_phy_ready(struct edp_phy *phy)
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{
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u32 status;
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int cnt = 100;
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while (--cnt) {
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status = edp_read(phy->base +
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REG_EDP_PHY_GLB_PHY_STATUS);
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if (status & 0x01)
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break;
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usleep_range(500, 1000);
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}
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if (cnt == 0) {
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pr_err("%s: PHY NOT ready\n", __func__);
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return false;
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} else {
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return true;
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}
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}
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void msm_edp_phy_ctrl(struct edp_phy *phy, int enable)
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{
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DBG("enable=%d", enable);
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if (enable) {
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/* Reset */
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edp_write(phy->base + REG_EDP_PHY_CTRL,
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EDP_PHY_CTRL_SW_RESET | EDP_PHY_CTRL_SW_RESET_PLL);
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/* Make sure fully reset */
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wmb();
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usleep_range(500, 1000);
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edp_write(phy->base + REG_EDP_PHY_CTRL, 0x000);
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edp_write(phy->base + REG_EDP_PHY_GLB_PD_CTL, 0x3f);
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edp_write(phy->base + REG_EDP_PHY_GLB_CFG, 0x1);
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} else {
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edp_write(phy->base + REG_EDP_PHY_GLB_PD_CTL, 0xc0);
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}
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}
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/* voltage mode and pre emphasis cfg */
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void msm_edp_phy_vm_pe_init(struct edp_phy *phy)
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{
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edp_write(phy->base + REG_EDP_PHY_GLB_VM_CFG0, 0x3);
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edp_write(phy->base + REG_EDP_PHY_GLB_VM_CFG1, 0x64);
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edp_write(phy->base + REG_EDP_PHY_GLB_MISC9, 0x6c);
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}
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void msm_edp_phy_vm_pe_cfg(struct edp_phy *phy, u32 v0, u32 v1)
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{
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edp_write(phy->base + REG_EDP_PHY_GLB_VM_CFG0, v0);
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edp_write(phy->base + REG_EDP_PHY_GLB_VM_CFG1, v1);
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}
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void msm_edp_phy_lane_power_ctrl(struct edp_phy *phy, bool up, u32 max_lane)
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{
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u32 i;
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u32 data;
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if (up)
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data = 0; /* power up */
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else
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data = 0x7; /* power down */
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for (i = 0; i < max_lane; i++)
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edp_write(phy->base + REG_EDP_PHY_LN_PD_CTL(i) , data);
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/* power down unused lane */
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data = 0x7; /* power down */
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for (i = max_lane; i < EDP_MAX_LANE; i++)
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edp_write(phy->base + REG_EDP_PHY_LN_PD_CTL(i) , data);
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}
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void *msm_edp_phy_init(struct device *dev, void __iomem *regbase)
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{
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struct edp_phy *phy = NULL;
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phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
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if (!phy)
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return NULL;
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phy->base = regbase;
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return phy;
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}
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