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Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
118 lines
3.2 KiB
C
118 lines
3.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Freescale SPI/eSPI controller driver library.
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*
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* Maintainer: Kumar Gala
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*
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* Copyright 2010 Freescale Semiconductor, Inc.
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* Copyright (C) 2006 Polycom, Inc.
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*
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* CPM SPI and QE buffer descriptors mode support:
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* Copyright (c) 2009 MontaVista Software, Inc.
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* Author: Anton Vorontsov <avorontsov@ru.mvista.com>
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*/
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#ifndef __SPI_FSL_LIB_H__
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#define __SPI_FSL_LIB_H__
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#include <asm/io.h>
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/* SPI/eSPI Controller driver's private data. */
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struct mpc8xxx_spi {
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struct device *dev;
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void __iomem *reg_base;
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/* rx & tx bufs from the spi_transfer */
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const void *tx;
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void *rx;
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int subblock;
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struct spi_pram __iomem *pram;
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#ifdef CONFIG_FSL_SOC
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struct cpm_buf_desc __iomem *tx_bd;
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struct cpm_buf_desc __iomem *rx_bd;
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#endif
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struct spi_transfer *xfer_in_progress;
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/* dma addresses for CPM transfers */
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dma_addr_t tx_dma;
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dma_addr_t rx_dma;
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bool map_tx_dma;
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bool map_rx_dma;
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dma_addr_t dma_dummy_tx;
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dma_addr_t dma_dummy_rx;
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/* functions to deal with different sized buffers */
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void (*get_rx) (u32 rx_data, struct mpc8xxx_spi *);
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u32(*get_tx) (struct mpc8xxx_spi *);
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unsigned int count;
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unsigned int irq;
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unsigned nsecs; /* (clock cycle time)/2 */
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u32 spibrg; /* SPIBRG input clock */
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u32 rx_shift; /* RX data reg shift when in qe mode */
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u32 tx_shift; /* TX data reg shift when in qe mode */
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unsigned int flags;
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#if IS_ENABLED(CONFIG_SPI_FSL_SPI)
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int type;
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int native_chipselects;
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u8 max_bits_per_word;
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void (*set_shifts)(u32 *rx_shift, u32 *tx_shift,
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int bits_per_word, int msb_first);
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#endif
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struct completion done;
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};
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struct spi_mpc8xxx_cs {
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/* functions to deal with different sized buffers */
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void (*get_rx) (u32 rx_data, struct mpc8xxx_spi *);
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u32 (*get_tx) (struct mpc8xxx_spi *);
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u32 rx_shift; /* RX data reg shift when in qe mode */
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u32 tx_shift; /* TX data reg shift when in qe mode */
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u32 hw_mode; /* Holds HW mode register settings */
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};
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static inline void mpc8xxx_spi_write_reg(__be32 __iomem *reg, u32 val)
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{
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iowrite32be(val, reg);
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}
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static inline u32 mpc8xxx_spi_read_reg(__be32 __iomem *reg)
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{
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return ioread32be(reg);
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}
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struct mpc8xxx_spi_probe_info {
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struct fsl_spi_platform_data pdata;
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int ngpios;
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int *gpios;
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bool *alow_flags;
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__be32 __iomem *immr_spi_cs;
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};
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extern u32 mpc8xxx_spi_tx_buf_u8(struct mpc8xxx_spi *mpc8xxx_spi);
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extern u32 mpc8xxx_spi_tx_buf_u16(struct mpc8xxx_spi *mpc8xxx_spi);
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extern u32 mpc8xxx_spi_tx_buf_u32(struct mpc8xxx_spi *mpc8xxx_spi);
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extern void mpc8xxx_spi_rx_buf_u8(u32 data, struct mpc8xxx_spi *mpc8xxx_spi);
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extern void mpc8xxx_spi_rx_buf_u16(u32 data, struct mpc8xxx_spi *mpc8xxx_spi);
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extern void mpc8xxx_spi_rx_buf_u32(u32 data, struct mpc8xxx_spi *mpc8xxx_spi);
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extern struct mpc8xxx_spi_probe_info *to_of_pinfo(
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struct fsl_spi_platform_data *pdata);
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extern int mpc8xxx_spi_bufs(struct mpc8xxx_spi *mspi,
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struct spi_transfer *t, unsigned int len);
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extern const char *mpc8xxx_spi_strmode(unsigned int flags);
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extern void mpc8xxx_spi_probe(struct device *dev, struct resource *mem,
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unsigned int irq);
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extern int mpc8xxx_spi_remove(struct device *dev);
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extern int of_mpc8xxx_spi_probe(struct platform_device *ofdev);
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#endif /* __SPI_FSL_LIB_H__ */
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