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Pull timer core updates from Thomas Gleixner: "This time you get nothing really exciting: - A huge update to the sh* clocksource drivers - Support for two more ARM SoCs - Removal of the deprecated setup_sched_clock() API - The usual pile of fixlets all over the place" * 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (23 commits) clocksource: Add Freescale FlexTimer Module (FTM) timer support ARM: dts: vf610: Add Freescale FlexTimer Module timer node. clocksource: ftm: Add FlexTimer Module (FTM) Timer devicetree Documentation clocksource: sh_tmu: Remove unnecessary OOM messages clocksource: sh_mtu2: Remove unnecessary OOM messages clocksource: sh_cmt: Remove unnecessary OOM messages clocksource: em_sti: Remove unnecessary OOM messages clocksource: dw_apb_timer_of: Do not trace read_sched_clock clocksource: Fix clocksource_mmio_readX_down clocksource: Fix type confusion for clocksource_mmio_readX_Y clocksource: sh_tmu: Fix channel IRQ retrieval in legacy case clocksource: qcom: Implement read_current_timer for udelay ntp: Make is_error_status() use its argument ntp: Convert simple_strtol to kstrtol timer_stats/doc: Fix /proc/timer_stats documentation sched_clock: Remove deprecated setup_sched_clock() API ARM: sun6i: a31: Add support for the High Speed Timers clocksource: sun5i: Add support for reset controller clocksource: efm32: use $vendor,$device scheme for compatible string KConfig: Vexpress: build the ARM_GLOBAL_TIMER with vexpress platform ...
87 lines
2.7 KiB
Plaintext
87 lines
2.7 KiB
Plaintext
config ARCH_VEXPRESS
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bool "ARM Ltd. Versatile Express family" if ARCH_MULTI_V7
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select ARCH_REQUIRE_GPIOLIB
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select ARCH_SUPPORTS_BIG_ENDIAN
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select ARM_AMBA
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select ARM_GIC
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select ARM_GLOBAL_TIMER
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select ARM_TIMER_SP804
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select COMMON_CLK_VERSATILE
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select HAVE_ARM_SCU if SMP
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select HAVE_ARM_TWD if SMP
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select HAVE_PATA_PLATFORM
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select ICST
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select NO_IOPORT_MAP
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select PLAT_VERSATILE
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select PLAT_VERSATILE_CLCD
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select POWER_RESET
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select POWER_RESET_VEXPRESS
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select POWER_SUPPLY
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select REGULATOR_FIXED_VOLTAGE if REGULATOR
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select VEXPRESS_CONFIG
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select VEXPRESS_SYSCFG
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select MFD_VEXPRESS_SYSREG
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help
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This option enables support for systems using Cortex processor based
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ARM core and logic (FPGA) tiles on the Versatile Express motherboard,
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for example:
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- CoreTile Express A5x2 (V2P-CA5s)
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- CoreTile Express A9x4 (V2P-CA9)
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- CoreTile Express A15x2 (V2P-CA15)
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- LogicTile Express 13MG (V2F-2XV6) with A5, A7, A9 or A15 SMMs
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(Soft Macrocell Models)
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- Versatile Express RTSMs (Models)
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You must boot using a Flattened Device Tree in order to use these
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platforms. The traditional (ATAGs) boot method is not usable on
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these boards with this option.
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menu "Versatile Express platform type"
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depends on ARCH_VEXPRESS
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config ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
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bool "Enable A5 and A9 only errata work-arounds"
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default y
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select ARM_ERRATA_720789
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select PL310_ERRATA_753970 if CACHE_PL310
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help
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Provides common dependencies for Versatile Express platforms
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based on Cortex-A5 and Cortex-A9 processors. In order to
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build a working kernel, you must also enable relevant core
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tile support or Flattened Device Tree based support options.
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config ARCH_VEXPRESS_CA9X4
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bool "Versatile Express Cortex-A9x4 tile"
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config ARCH_VEXPRESS_DCSCB
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bool "Dual Cluster System Control Block (DCSCB) support"
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depends on MCPM
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select ARM_CCI
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help
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Support for the Dual Cluster System Configuration Block (DCSCB).
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This is needed to provide CPU and cluster power management
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on RTSM implementing big.LITTLE.
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config ARCH_VEXPRESS_SPC
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bool "Versatile Express Serial Power Controller (SPC)"
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select ARCH_HAS_CPUFREQ
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select ARCH_HAS_OPP
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select PM_OPP
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help
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The TC2 (A15x2 A7x3) versatile express core tile integrates a logic
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block called Serial Power Controller (SPC) that provides the interface
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between the dual cluster test-chip and the M3 microcontroller that
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carries out power management.
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config ARCH_VEXPRESS_TC2_PM
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bool "Versatile Express TC2 power management"
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depends on MCPM
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select ARM_CCI
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select ARCH_VEXPRESS_SPC
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help
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Support for CPU and cluster power management on Versatile Express
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with a TC2 (A15x2 A7x3) big.LITTLE core tile.
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endmenu
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