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8c16babc64
The cpuidle is a platform driver so we register the device just after the initialization of the board in an arch_initcall. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Link: https://lkml.kernel.org/r/1397488214-20685-12-git-send-email-gregory.clement@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
299 lines
8.2 KiB
C
299 lines
8.2 KiB
C
/*
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* Power Management Service Unit(PMSU) support for Armada 370/XP platforms.
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*
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* Copyright (C) 2012 Marvell
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*
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* Yehuda Yitschak <yehuday@marvell.com>
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* Gregory Clement <gregory.clement@free-electrons.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*
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* The Armada 370 and Armada XP SOCs have a power management service
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* unit which is responsible for powering down and waking up CPUs and
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* other SOC units
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*/
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#define pr_fmt(fmt) "mvebu-pmsu: " fmt
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#include <linux/cpu_pm.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/of_address.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <linux/smp.h>
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#include <linux/resource.h>
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#include <asm/cacheflush.h>
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#include <asm/cp15.h>
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#include <asm/smp_plat.h>
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#include <asm/suspend.h>
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#include <asm/tlbflush.h>
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#include "common.h"
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static void __iomem *pmsu_mp_base;
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#define PMSU_BASE_OFFSET 0x100
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#define PMSU_REG_SIZE 0x1000
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/* PMSU MP registers */
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#define PMSU_CONTROL_AND_CONFIG(cpu) ((cpu * 0x100) + 0x104)
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#define PMSU_CONTROL_AND_CONFIG_DFS_REQ BIT(18)
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#define PMSU_CONTROL_AND_CONFIG_PWDDN_REQ BIT(16)
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#define PMSU_CONTROL_AND_CONFIG_L2_PWDDN BIT(20)
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#define PMSU_CPU_POWER_DOWN_CONTROL(cpu) ((cpu * 0x100) + 0x108)
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#define PMSU_CPU_POWER_DOWN_DIS_SNP_Q_SKIP BIT(0)
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#define PMSU_STATUS_AND_MASK(cpu) ((cpu * 0x100) + 0x10c)
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#define PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT BIT(16)
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#define PMSU_STATUS_AND_MASK_SNP_Q_EMPTY_WAIT BIT(17)
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#define PMSU_STATUS_AND_MASK_IRQ_WAKEUP BIT(20)
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#define PMSU_STATUS_AND_MASK_FIQ_WAKEUP BIT(21)
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#define PMSU_STATUS_AND_MASK_DBG_WAKEUP BIT(22)
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#define PMSU_STATUS_AND_MASK_IRQ_MASK BIT(24)
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#define PMSU_STATUS_AND_MASK_FIQ_MASK BIT(25)
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#define PMSU_BOOT_ADDR_REDIRECT_OFFSET(cpu) ((cpu * 0x100) + 0x124)
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/* PMSU fabric registers */
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#define L2C_NFABRIC_PM_CTL 0x4
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#define L2C_NFABRIC_PM_CTL_PWR_DOWN BIT(20)
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extern void ll_disable_coherency(void);
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extern void ll_enable_coherency(void);
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static struct platform_device armada_xp_cpuidle_device = {
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.name = "cpuidle-armada-370-xp",
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};
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static struct of_device_id of_pmsu_table[] = {
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{ .compatible = "marvell,armada-370-pmsu", },
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{ .compatible = "marvell,armada-370-xp-pmsu", },
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{ .compatible = "marvell,armada-380-pmsu", },
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{ /* end of list */ },
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};
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void mvebu_pmsu_set_cpu_boot_addr(int hw_cpu, void *boot_addr)
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{
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writel(virt_to_phys(boot_addr), pmsu_mp_base +
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PMSU_BOOT_ADDR_REDIRECT_OFFSET(hw_cpu));
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}
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static int __init armada_370_xp_pmsu_init(void)
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{
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struct device_node *np;
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struct resource res;
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int ret = 0;
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np = of_find_matching_node(NULL, of_pmsu_table);
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if (!np)
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return 0;
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pr_info("Initializing Power Management Service Unit\n");
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if (of_address_to_resource(np, 0, &res)) {
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pr_err("unable to get resource\n");
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ret = -ENOENT;
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goto out;
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}
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if (of_device_is_compatible(np, "marvell,armada-370-xp-pmsu")) {
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pr_warn(FW_WARN "deprecated pmsu binding\n");
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res.start = res.start - PMSU_BASE_OFFSET;
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res.end = res.start + PMSU_REG_SIZE - 1;
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}
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if (!request_mem_region(res.start, resource_size(&res),
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np->full_name)) {
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pr_err("unable to request region\n");
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ret = -EBUSY;
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goto out;
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}
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pmsu_mp_base = ioremap(res.start, resource_size(&res));
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if (!pmsu_mp_base) {
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pr_err("unable to map registers\n");
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release_mem_region(res.start, resource_size(&res));
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ret = -ENOMEM;
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goto out;
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}
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out:
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of_node_put(np);
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return ret;
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}
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static void armada_370_xp_pmsu_enable_l2_powerdown_onidle(void)
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{
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u32 reg;
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if (pmsu_mp_base == NULL)
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return;
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/* Enable L2 & Fabric powerdown in Deep-Idle mode - Fabric */
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reg = readl(pmsu_mp_base + L2C_NFABRIC_PM_CTL);
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reg |= L2C_NFABRIC_PM_CTL_PWR_DOWN;
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writel(reg, pmsu_mp_base + L2C_NFABRIC_PM_CTL);
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}
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static void armada_370_xp_cpu_resume(void)
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{
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asm volatile("bl ll_add_cpu_to_smp_group\n\t"
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"bl ll_enable_coherency\n\t"
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"b cpu_resume\n\t");
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}
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/* No locking is needed because we only access per-CPU registers */
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void armada_370_xp_pmsu_idle_prepare(bool deepidle)
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{
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unsigned int hw_cpu = cpu_logical_map(smp_processor_id());
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u32 reg;
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if (pmsu_mp_base == NULL)
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return;
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/*
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* Adjust the PMSU configuration to wait for WFI signal, enable
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* IRQ and FIQ as wakeup events, set wait for snoop queue empty
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* indication and mask IRQ and FIQ from CPU
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*/
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reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu));
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reg |= PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT |
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PMSU_STATUS_AND_MASK_IRQ_WAKEUP |
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PMSU_STATUS_AND_MASK_FIQ_WAKEUP |
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PMSU_STATUS_AND_MASK_SNP_Q_EMPTY_WAIT |
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PMSU_STATUS_AND_MASK_IRQ_MASK |
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PMSU_STATUS_AND_MASK_FIQ_MASK;
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writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu));
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reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));
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/* ask HW to power down the L2 Cache if needed */
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if (deepidle)
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reg |= PMSU_CONTROL_AND_CONFIG_L2_PWDDN;
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/* request power down */
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reg |= PMSU_CONTROL_AND_CONFIG_PWDDN_REQ;
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writel(reg, pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));
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/* Disable snoop disable by HW - SW is taking care of it */
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reg = readl(pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu));
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reg |= PMSU_CPU_POWER_DOWN_DIS_SNP_Q_SKIP;
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writel(reg, pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu));
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}
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static noinline int do_armada_370_xp_cpu_suspend(unsigned long deepidle)
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{
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armada_370_xp_pmsu_idle_prepare(deepidle);
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v7_exit_coherency_flush(all);
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ll_disable_coherency();
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dsb();
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wfi();
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/* If we are here, wfi failed. As processors run out of
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* coherency for some time, tlbs might be stale, so flush them
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*/
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local_flush_tlb_all();
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ll_enable_coherency();
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/* Test the CR_C bit and set it if it was cleared */
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asm volatile(
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"mrc p15, 0, %0, c1, c0, 0 \n\t"
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"tst %0, #(1 << 2) \n\t"
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"orreq %0, %0, #(1 << 2) \n\t"
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"mcreq p15, 0, %0, c1, c0, 0 \n\t"
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"isb "
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: : "r" (0));
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pr_warn("Failed to suspend the system\n");
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return 0;
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}
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static int armada_370_xp_cpu_suspend(unsigned long deepidle)
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{
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return cpu_suspend(deepidle, do_armada_370_xp_cpu_suspend);
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}
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/* No locking is needed because we only access per-CPU registers */
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static noinline void armada_370_xp_pmsu_idle_restore(void)
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{
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unsigned int hw_cpu = cpu_logical_map(smp_processor_id());
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u32 reg;
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if (pmsu_mp_base == NULL)
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return;
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/* cancel ask HW to power down the L2 Cache if possible */
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reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));
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reg &= ~PMSU_CONTROL_AND_CONFIG_L2_PWDDN;
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writel(reg, pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));
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/* cancel Enable wakeup events and mask interrupts */
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reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu));
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reg &= ~(PMSU_STATUS_AND_MASK_IRQ_WAKEUP | PMSU_STATUS_AND_MASK_FIQ_WAKEUP);
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reg &= ~PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT;
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reg &= ~PMSU_STATUS_AND_MASK_SNP_Q_EMPTY_WAIT;
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reg &= ~(PMSU_STATUS_AND_MASK_IRQ_MASK | PMSU_STATUS_AND_MASK_FIQ_MASK);
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writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu));
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}
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static int armada_370_xp_cpu_pm_notify(struct notifier_block *self,
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unsigned long action, void *hcpu)
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{
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if (action == CPU_PM_ENTER) {
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unsigned int hw_cpu = cpu_logical_map(smp_processor_id());
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mvebu_pmsu_set_cpu_boot_addr(hw_cpu, armada_370_xp_cpu_resume);
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} else if (action == CPU_PM_EXIT) {
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armada_370_xp_pmsu_idle_restore();
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}
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return NOTIFY_OK;
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}
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static struct notifier_block armada_370_xp_cpu_pm_notifier = {
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.notifier_call = armada_370_xp_cpu_pm_notify,
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};
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int __init armada_370_xp_cpu_pm_init(void)
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{
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struct device_node *np;
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/*
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* Check that all the requirements are available to enable
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* cpuidle. So far, it is only supported on Armada XP, cpuidle
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* needs the coherency fabric and the PMSU enabled
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*/
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if (!of_machine_is_compatible("marvell,armadaxp"))
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return 0;
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np = of_find_compatible_node(NULL, NULL, "marvell,coherency-fabric");
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if (!np)
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return 0;
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of_node_put(np);
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np = of_find_matching_node(NULL, of_pmsu_table);
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if (!np)
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return 0;
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of_node_put(np);
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armada_370_xp_pmsu_enable_l2_powerdown_onidle();
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armada_xp_cpuidle_device.dev.platform_data = armada_370_xp_cpu_suspend;
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platform_device_register(&armada_xp_cpuidle_device);
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cpu_pm_register_notifier(&armada_370_xp_cpu_pm_notifier);
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return 0;
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}
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arch_initcall(armada_370_xp_cpu_pm_init);
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early_initcall(armada_370_xp_pmsu_init);
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