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6e90889202
The core support for the pinctrl drivers for all the UniPhier SoCs.
Changes in v2:
- drop vogus THIS_MODULE because this file is always built-in
- drop vogus "include <linux/module.h> because this file is
always built-in
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
218 lines
6.8 KiB
C
218 lines
6.8 KiB
C
/*
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* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __PINCTRL_UNIPHIER_H__
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#define __PINCTRL_UNIPHIER_H__
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#include <linux/bug.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#define UNIPHIER_PINCTRL_PINMUX_BASE 0x0
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#define UNIPHIER_PINCTRL_LOAD_PINMUX 0x700
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#define UNIPHIER_PINCTRL_DRVCTRL_BASE 0x800
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#define UNIPHIER_PINCTRL_DRV2CTRL_BASE 0x900
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#define UNIPHIER_PINCTRL_PUPDCTRL_BASE 0xa00
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#define UNIPHIER_PINCTRL_IECTRL 0xd00
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/* input enable control register bit */
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#define UNIPHIER_PIN_IECTRL_SHIFT 0
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#define UNIPHIER_PIN_IECTRL_BITS 8
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#define UNIPHIER_PIN_IECTRL_MASK ((1UL << (UNIPHIER_PIN_IECTRL_BITS)) \
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- 1)
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/* drive strength control register number */
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#define UNIPHIER_PIN_DRVCTRL_SHIFT ((UNIPHIER_PIN_IECTRL_SHIFT) + \
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(UNIPHIER_PIN_IECTRL_BITS))
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#define UNIPHIER_PIN_DRVCTRL_BITS 9
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#define UNIPHIER_PIN_DRVCTRL_MASK ((1UL << (UNIPHIER_PIN_DRVCTRL_BITS)) \
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- 1)
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/* supported drive strength (mA) */
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#define UNIPHIER_PIN_DRV_STR_SHIFT ((UNIPHIER_PIN_DRVCTRL_SHIFT) + \
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(UNIPHIER_PIN_DRVCTRL_BITS))
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#define UNIPHIER_PIN_DRV_STR_BITS 3
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#define UNIPHIER_PIN_DRV_STR_MASK ((1UL << (UNIPHIER_PIN_DRV_STR_BITS)) \
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- 1)
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/* pull-up / pull-down register number */
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#define UNIPHIER_PIN_PUPDCTRL_SHIFT ((UNIPHIER_PIN_DRV_STR_SHIFT) + \
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(UNIPHIER_PIN_DRV_STR_BITS))
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#define UNIPHIER_PIN_PUPDCTRL_BITS 9
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#define UNIPHIER_PIN_PUPDCTRL_MASK ((1UL << (UNIPHIER_PIN_PUPDCTRL_BITS))\
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- 1)
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/* direction of pull register */
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#define UNIPHIER_PIN_PULL_DIR_SHIFT ((UNIPHIER_PIN_PUPDCTRL_SHIFT) + \
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(UNIPHIER_PIN_PUPDCTRL_BITS))
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#define UNIPHIER_PIN_PULL_DIR_BITS 3
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#define UNIPHIER_PIN_PULL_DIR_MASK ((1UL << (UNIPHIER_PIN_PULL_DIR_BITS))\
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- 1)
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#if UNIPHIER_PIN_PULL_DIR_SHIFT + UNIPHIER_PIN_PULL_DIR_BITS > BITS_PER_LONG
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#error "unable to pack pin attributes."
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#endif
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#define UNIPHIER_PIN_IECTRL_NONE (UNIPHIER_PIN_IECTRL_MASK)
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/* selectable drive strength */
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enum uniphier_pin_drv_str {
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UNIPHIER_PIN_DRV_4_8, /* 2 level control: 4/8 mA */
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UNIPHIER_PIN_DRV_8_12_16_20, /* 4 level control: 8/12/16/20 mA */
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UNIPHIER_PIN_DRV_FIXED_4, /* fixed to 4mA */
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UNIPHIER_PIN_DRV_FIXED_5, /* fixed to 5mA */
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UNIPHIER_PIN_DRV_FIXED_8, /* fixed to 8mA */
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UNIPHIER_PIN_DRV_NONE, /* no support (input only pin) */
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};
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/* direction of pull register (no pin supports bi-directional pull biasing) */
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enum uniphier_pin_pull_dir {
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UNIPHIER_PIN_PULL_UP, /* pull-up or disabled */
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UNIPHIER_PIN_PULL_DOWN, /* pull-down or disabled */
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UNIPHIER_PIN_PULL_UP_FIXED, /* always pull-up */
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UNIPHIER_PIN_PULL_DOWN_FIXED, /* always pull-down */
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UNIPHIER_PIN_PULL_NONE, /* no pull register */
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};
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#define UNIPHIER_PIN_IECTRL(x) \
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(((x) & (UNIPHIER_PIN_IECTRL_MASK)) << (UNIPHIER_PIN_IECTRL_SHIFT))
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#define UNIPHIER_PIN_DRVCTRL(x) \
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(((x) & (UNIPHIER_PIN_DRVCTRL_MASK)) << (UNIPHIER_PIN_DRVCTRL_SHIFT))
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#define UNIPHIER_PIN_DRV_STR(x) \
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(((x) & (UNIPHIER_PIN_DRV_STR_MASK)) << (UNIPHIER_PIN_DRV_STR_SHIFT))
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#define UNIPHIER_PIN_PUPDCTRL(x) \
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(((x) & (UNIPHIER_PIN_PUPDCTRL_MASK)) << (UNIPHIER_PIN_PUPDCTRL_SHIFT))
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#define UNIPHIER_PIN_PULL_DIR(x) \
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(((x) & (UNIPHIER_PIN_PULL_DIR_MASK)) << (UNIPHIER_PIN_PULL_DIR_SHIFT))
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#define UNIPHIER_PIN_ATTR_PACKED(iectrl, drvctrl, drv_str, pupdctrl, pull_dir)\
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(UNIPHIER_PIN_IECTRL(iectrl) | \
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UNIPHIER_PIN_DRVCTRL(drvctrl) | \
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UNIPHIER_PIN_DRV_STR(drv_str) | \
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UNIPHIER_PIN_PUPDCTRL(pupdctrl) | \
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UNIPHIER_PIN_PULL_DIR(pull_dir))
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static inline unsigned int uniphier_pin_get_iectrl(void *drv_data)
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{
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return ((unsigned long)drv_data >> UNIPHIER_PIN_IECTRL_SHIFT) &
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UNIPHIER_PIN_IECTRL_MASK;
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}
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static inline unsigned int uniphier_pin_get_drvctrl(void *drv_data)
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{
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return ((unsigned long)drv_data >> UNIPHIER_PIN_DRVCTRL_SHIFT) &
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UNIPHIER_PIN_DRVCTRL_MASK;
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}
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static inline unsigned int uniphier_pin_get_drv_str(void *drv_data)
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{
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return ((unsigned long)drv_data >> UNIPHIER_PIN_DRV_STR_SHIFT) &
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UNIPHIER_PIN_DRV_STR_MASK;
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}
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static inline unsigned int uniphier_pin_get_pupdctrl(void *drv_data)
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{
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return ((unsigned long)drv_data >> UNIPHIER_PIN_PUPDCTRL_SHIFT) &
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UNIPHIER_PIN_PUPDCTRL_MASK;
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}
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static inline unsigned int uniphier_pin_get_pull_dir(void *drv_data)
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{
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return ((unsigned long)drv_data >> UNIPHIER_PIN_PULL_DIR_SHIFT) &
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UNIPHIER_PIN_PULL_DIR_MASK;
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}
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enum uniphier_pinmux_gpio_range_type {
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UNIPHIER_PINMUX_GPIO_RANGE_PORT,
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UNIPHIER_PINMUX_GPIO_RANGE_IRQ,
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UNIPHIER_PINMUX_GPIO_RANGE_NONE,
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};
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struct uniphier_pinctrl_group {
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const char *name;
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const unsigned *pins;
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unsigned num_pins;
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const unsigned *muxvals;
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enum uniphier_pinmux_gpio_range_type range_type;
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};
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struct uniphier_pinmux_function {
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const char *name;
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const char * const *groups;
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unsigned num_groups;
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};
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struct uniphier_pinctrl_socdata {
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const struct uniphier_pinctrl_group *groups;
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int groups_count;
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const struct uniphier_pinmux_function *functions;
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int functions_count;
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unsigned mux_bits;
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unsigned reg_stride;
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bool load_pinctrl;
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};
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#define UNIPHIER_PINCTRL_PIN(a, b, c, d, e, f, g) \
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{ \
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.number = a, \
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.name = b, \
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.drv_data = (void *)UNIPHIER_PIN_ATTR_PACKED(c, d, e, f, g), \
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}
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#define __UNIPHIER_PINCTRL_GROUP(grp, type) \
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{ \
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.name = #grp, \
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.pins = grp##_pins, \
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.num_pins = ARRAY_SIZE(grp##_pins), \
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.muxvals = grp##_muxvals + \
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BUILD_BUG_ON_ZERO(ARRAY_SIZE(grp##_pins) != \
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ARRAY_SIZE(grp##_muxvals)), \
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.range_type = type, \
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}
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#define UNIPHIER_PINCTRL_GROUP(grp) \
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__UNIPHIER_PINCTRL_GROUP(grp, UNIPHIER_PINMUX_GPIO_RANGE_NONE)
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#define UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(grp) \
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__UNIPHIER_PINCTRL_GROUP(grp, UNIPHIER_PINMUX_GPIO_RANGE_PORT)
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#define UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(grp) \
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__UNIPHIER_PINCTRL_GROUP(grp, UNIPHIER_PINMUX_GPIO_RANGE_IRQ)
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#define UNIPHIER_PINCTRL_GROUP_SINGLE(grp, array, ofst) \
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{ \
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.name = #grp, \
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.pins = array##_pins + ofst, \
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.num_pins = 1, \
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.muxvals = array##_muxvals + ofst, \
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}
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#define UNIPHIER_PINMUX_FUNCTION(func) \
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{ \
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.name = #func, \
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.groups = func##_groups, \
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.num_groups = ARRAY_SIZE(func##_groups), \
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}
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struct platform_device;
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struct pinctrl_desc;
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int uniphier_pinctrl_probe(struct platform_device *pdev,
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struct pinctrl_desc *desc,
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struct uniphier_pinctrl_socdata *socdata);
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int uniphier_pinctrl_remove(struct platform_device *pdev);
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#endif /* __PINCTRL_UNIPHIER_H__ */
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