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e68f31f452
This adds support for the Marvell Tauros3 cache controller which is compatible with pl310 cache controller but broadcasts L1 cache operations to L2 cache. While updating the binding documentation, clean up the list of possible compatibles. Also reorder driver compatibles to allow non-ARM derivated to be compatible to ARM cache controller compatibles. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
42 lines
1.3 KiB
C
42 lines
1.3 KiB
C
/*
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* Marvell Tauros3 cache controller includes
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*
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* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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*
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* based on GPL'ed 2.6 kernel sources
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* (c) Marvell International Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef __ASM_ARM_HARDWARE_TAUROS3_H
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#define __ASM_ARM_HARDWARE_TAUROS3_H
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/*
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* Marvell Tauros3 L2CC is compatible with PL310 r0p0
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* but with PREFETCH_CTRL (r2p0) and an additional event counter.
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* Also, there is AUX2_CTRL for some Marvell specific control.
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*/
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#define TAUROS3_EVENT_CNT2_CFG 0x224
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#define TAUROS3_EVENT_CNT2_VAL 0x228
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#define TAUROS3_INV_ALL 0x780
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#define TAUROS3_CLEAN_ALL 0x784
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#define TAUROS3_AUX2_CTRL 0x820
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/* Registers shifts and masks */
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#define TAUROS3_AUX2_CTRL_LINEFILL_BURST8_EN (1 << 2)
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#endif
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