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1484276119
Add the ADSP clock support to the R-Car generation 2 CPG driver. This clock gets derived from PLL1. The layout of the ADSPCKCR register is similar to those of the clocks supported by the 'clk-div6' driver but the divider encoding is non-linear, so can't be supported by that driver... Based on the original patch by Konstantin Kozhevnikov <konstantin.kozhevnikov@cogentembedded.com>. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
38 lines
1.2 KiB
Plaintext
38 lines
1.2 KiB
Plaintext
* Renesas R-Car Gen2 Clock Pulse Generator (CPG)
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The CPG generates core clocks for the R-Car Gen2 SoCs. It includes three PLLs
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and several fixed ratio dividers.
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Required Properties:
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- compatible: Must be one of
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- "renesas,r8a7790-cpg-clocks" for the r8a7790 CPG
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- "renesas,r8a7791-cpg-clocks" for the r8a7791 CPG
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- "renesas,r8a7793-cpg-clocks" for the r8a7793 CPG
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- "renesas,r8a7794-cpg-clocks" for the r8a7794 CPG
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- "renesas,rcar-gen2-cpg-clocks" for the generic R-Car Gen2 CPG
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- reg: Base address and length of the memory resource used by the CPG
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- clocks: References to the parent clocks: first to the EXTAL clock, second
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to the USB_EXTAL clock
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- #clock-cells: Must be 1
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- clock-output-names: The names of the clocks. Supported clocks are "main",
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"pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "sd1", "z", "rcan", and
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"adsp"
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Example
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-------
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cpg_clocks: cpg_clocks@e6150000 {
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compatible = "renesas,r8a7790-cpg-clocks",
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"renesas,rcar-gen2-cpg-clocks";
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reg = <0 0xe6150000 0 0x1000>;
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clocks = <&extal_clk &usb_extal_clk>;
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#clock-cells = <1>;
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clock-output-names = "main", "pll0, "pll1", "pll3",
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"lb", "qspi", "sdh", "sd0", "sd1", "z",
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"rcan", "adsp";
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};
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