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106267444f
Add driver for the Image Sensor Controller. It manages incoming data from a parallel based CMOS/CCD sensor. It has an internal image processor, also integrates a triple channel direct memory access controller master interface. Signed-off-by: Songjun Wu <songjun.wu@microchip.com> Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
166 lines
4.9 KiB
C
166 lines
4.9 KiB
C
#ifndef __ATMEL_ISC_REGS_H
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#define __ATMEL_ISC_REGS_H
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#include <linux/bitops.h>
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/* ISC Control Enable Register 0 */
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#define ISC_CTRLEN 0x00000000
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/* ISC Control Disable Register 0 */
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#define ISC_CTRLDIS 0x00000004
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/* ISC Control Status Register 0 */
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#define ISC_CTRLSR 0x00000008
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#define ISC_CTRL_CAPTURE BIT(0)
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#define ISC_CTRL_UPPRO BIT(1)
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#define ISC_CTRL_HISREQ BIT(2)
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#define ISC_CTRL_HISCLR BIT(3)
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/* ISC Parallel Front End Configuration 0 Register */
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#define ISC_PFE_CFG0 0x0000000c
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#define ISC_PFE_CFG0_HPOL_LOW BIT(0)
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#define ISC_PFE_CFG0_VPOL_LOW BIT(1)
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#define ISC_PFE_CFG0_PPOL_LOW BIT(2)
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#define ISC_PFE_CFG0_MODE_PROGRESSIVE (0x0 << 4)
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#define ISC_PFE_CFG0_MODE_MASK GENMASK(6, 4)
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#define ISC_PFE_CFG0_BPS_EIGHT (0x4 << 28)
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#define ISC_PFG_CFG0_BPS_NINE (0x3 << 28)
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#define ISC_PFG_CFG0_BPS_TEN (0x2 << 28)
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#define ISC_PFG_CFG0_BPS_ELEVEN (0x1 << 28)
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#define ISC_PFG_CFG0_BPS_TWELVE (0x0 << 28)
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#define ISC_PFE_CFG0_BPS_MASK GENMASK(30, 28)
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/* ISC Clock Enable Register */
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#define ISC_CLKEN 0x00000018
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/* ISC Clock Disable Register */
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#define ISC_CLKDIS 0x0000001c
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/* ISC Clock Status Register */
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#define ISC_CLKSR 0x00000020
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#define ISC_CLK(n) BIT(n)
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/* ISC Clock Configuration Register */
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#define ISC_CLKCFG 0x00000024
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#define ISC_CLKCFG_DIV_SHIFT(n) ((n)*16)
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#define ISC_CLKCFG_DIV_MASK(n) GENMASK(((n)*16 + 7), (n)*16)
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#define ISC_CLKCFG_SEL_SHIFT(n) ((n)*16 + 8)
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#define ISC_CLKCFG_SEL_MASK(n) GENMASK(((n)*17 + 8), ((n)*16 + 8))
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/* ISC Interrupt Enable Register */
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#define ISC_INTEN 0x00000028
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/* ISC Interrupt Disable Register */
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#define ISC_INTDIS 0x0000002c
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/* ISC Interrupt Mask Register */
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#define ISC_INTMASK 0x00000030
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/* ISC Interrupt Status Register */
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#define ISC_INTSR 0x00000034
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#define ISC_INT_DDONE BIT(8)
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/* ISC White Balance Control Register */
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#define ISC_WB_CTRL 0x00000058
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/* ISC White Balance Configuration Register */
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#define ISC_WB_CFG 0x0000005c
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/* ISC Color Filter Array Control Register */
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#define ISC_CFA_CTRL 0x00000070
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/* ISC Color Filter Array Configuration Register */
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#define ISC_CFA_CFG 0x00000074
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#define ISC_BAY_CFG_GRGR 0x0
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#define ISC_BAY_CFG_RGRG 0x1
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#define ISC_BAY_CFG_GBGB 0x2
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#define ISC_BAY_CFG_BGBG 0x3
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#define ISC_BAY_CFG_MASK GENMASK(1, 0)
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/* ISC Color Correction Control Register */
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#define ISC_CC_CTRL 0x00000078
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/* ISC Gamma Correction Control Register */
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#define ISC_GAM_CTRL 0x00000094
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/* Color Space Conversion Control Register */
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#define ISC_CSC_CTRL 0x00000398
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/* Contrast And Brightness Control Register */
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#define ISC_CBC_CTRL 0x000003b4
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/* Subsampling 4:4:4 to 4:2:2 Control Register */
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#define ISC_SUB422_CTRL 0x000003c4
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/* Subsampling 4:2:2 to 4:2:0 Control Register */
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#define ISC_SUB420_CTRL 0x000003cc
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/* Rounding, Limiting and Packing Configuration Register */
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#define ISC_RLP_CFG 0x000003d0
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#define ISC_RLP_CFG_MODE_DAT8 0x0
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#define ISC_RLP_CFG_MODE_DAT9 0x1
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#define ISC_RLP_CFG_MODE_DAT10 0x2
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#define ISC_RLP_CFG_MODE_DAT11 0x3
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#define ISC_RLP_CFG_MODE_DAT12 0x4
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#define ISC_RLP_CFG_MODE_DATY8 0x5
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#define ISC_RLP_CFG_MODE_DATY10 0x6
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#define ISC_RLP_CFG_MODE_ARGB444 0x7
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#define ISC_RLP_CFG_MODE_ARGB555 0x8
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#define ISC_RLP_CFG_MODE_RGB565 0x9
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#define ISC_RLP_CFG_MODE_ARGB32 0xa
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#define ISC_RLP_CFG_MODE_YYCC 0xb
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#define ISC_RLP_CFG_MODE_YYCC_LIMITED 0xc
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#define ISC_RLP_CFG_MODE_MASK GENMASK(3, 0)
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/* DMA Configuration Register */
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#define ISC_DCFG 0x000003e0
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#define ISC_DCFG_IMODE_PACKED8 0x0
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#define ISC_DCFG_IMODE_PACKED16 0x1
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#define ISC_DCFG_IMODE_PACKED32 0x2
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#define ISC_DCFG_IMODE_YC422SP 0x3
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#define ISC_DCFG_IMODE_YC422P 0x4
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#define ISC_DCFG_IMODE_YC420SP 0x5
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#define ISC_DCFG_IMODE_YC420P 0x6
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#define ISC_DCFG_IMODE_MASK GENMASK(2, 0)
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#define ISC_DCFG_YMBSIZE_SINGLE (0x0 << 4)
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#define ISC_DCFG_YMBSIZE_BEATS4 (0x1 << 4)
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#define ISC_DCFG_YMBSIZE_BEATS8 (0x2 << 4)
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#define ISC_DCFG_YMBSIZE_BEATS16 (0x3 << 4)
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#define ISC_DCFG_YMBSIZE_MASK GENMASK(5, 4)
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#define ISC_DCFG_CMBSIZE_SINGLE (0x0 << 8)
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#define ISC_DCFG_CMBSIZE_BEATS4 (0x1 << 8)
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#define ISC_DCFG_CMBSIZE_BEATS8 (0x2 << 8)
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#define ISC_DCFG_CMBSIZE_BEATS16 (0x3 << 8)
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#define ISC_DCFG_CMBSIZE_MASK GENMASK(9, 8)
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/* DMA Control Register */
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#define ISC_DCTRL 0x000003e4
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#define ISC_DCTRL_DVIEW_PACKED (0x0 << 1)
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#define ISC_DCTRL_DVIEW_SEMIPLANAR (0x1 << 1)
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#define ISC_DCTRL_DVIEW_PLANAR (0x2 << 1)
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#define ISC_DCTRL_DVIEW_MASK GENMASK(2, 1)
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#define ISC_DCTRL_IE_IS (0x0 << 4)
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/* DMA Descriptor Address Register */
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#define ISC_DNDA 0x000003e8
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/* DMA Address 0 Register */
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#define ISC_DAD0 0x000003ec
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/* DMA Stride 0 Register */
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#define ISC_DST0 0x000003f0
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#endif
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