Petri Gynther 23fbb5a87c emac: Fix EMAC soft reset on 460EX/GT ... Fix EMAC soft reset on 460EX/GT to select the right PHY clock source before and after the soft reset. EMAC with PHY should use the clock from PHY during soft reset. EMAC without PHY should use the internal clock during soft reset. PPC460EX/GT Embedded Processor Advanced User's Manual section 28.10.1 Mode Register 0 (EMACx_MR0) states: Note: The PHY must provide a TX Clk in order to perform a soft reset of the EMAC. If none is present, select the internal clock (SDR0_ETH_CFG[EMACx_PHY_CLK] = 1). After a soft reset, select the external clock. Without the fix, 460EX/GT-based boards with RGMII PHYs attached to EMACs experience EMAC interrupt storm and system watchdog reset when issuing "ifconfig eth0 down" + "ifconfig eth0 up" a few times. The system enters endless loop of serving emac_irq() with EMACx_ISR register stuck at value 0x10000000 (Rx parity error). With the fix, the above issue is no longer observed. Signed-off-by: Petri Gynther <pgynther@google.com> Signed-off-by: David S. Miller <davem@davemloft.net>		2013-05-11 17:40:14 -07:00
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ehea	net: Fix vlan bitmask changes in EHEA driver.	2013-04-22 19:34:34 -04:00
emac	emac: Fix EMAC soft reset on 460EX/GT	2013-05-11 17:40:14 -07:00
ibmveth.c	net/eth/ibmveth: Fixup retrieval of MAC address	2013-05-05 16:58:02 -04:00
ibmveth.h
Kconfig	ehea: Remove remnants of LRO support	2012-11-19 19:13:59 -05:00
Makefile	net: powerpc: remove the legacy iSeries ethernet driver	2012-03-09 23:41:26 -05:00