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6033cebdff
The type of loaddr is u8 which is always '<=' 0xff, so the loaddr <= 0xff is always true, we can remove this comparison. Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
1009 lines
21 KiB
C
1009 lines
21 KiB
C
// SPDX-License-Identifier: GPL-2.0
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//
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// Copyright (C) 2018 Integrated Device Technology, Inc
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//
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#define pr_fmt(fmt) "IDT_82p33xxx: " fmt
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#include <linux/firmware.h>
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#include <linux/i2c.h>
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#include <linux/module.h>
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#include <linux/ptp_clock_kernel.h>
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#include <linux/delay.h>
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#include <linux/kernel.h>
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#include <linux/timekeeping.h>
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#include <linux/bitops.h>
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#include "ptp_private.h"
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#include "ptp_idt82p33.h"
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MODULE_DESCRIPTION("Driver for IDT 82p33xxx clock devices");
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MODULE_AUTHOR("IDT support-1588 <IDT-support-1588@lm.renesas.com>");
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MODULE_VERSION("1.0");
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MODULE_LICENSE("GPL");
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/* Module Parameters */
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static u32 sync_tod_timeout = SYNC_TOD_TIMEOUT_SEC;
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module_param(sync_tod_timeout, uint, 0);
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MODULE_PARM_DESC(sync_tod_timeout,
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"duration in second to keep SYNC_TOD on (set to 0 to keep it always on)");
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static u32 phase_snap_threshold = SNAP_THRESHOLD_NS;
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module_param(phase_snap_threshold, uint, 0);
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MODULE_PARM_DESC(phase_snap_threshold,
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"threshold (150000ns by default) below which adjtime would ignore");
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static void idt82p33_byte_array_to_timespec(struct timespec64 *ts,
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u8 buf[TOD_BYTE_COUNT])
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{
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time64_t sec;
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s32 nsec;
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u8 i;
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nsec = buf[3];
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for (i = 0; i < 3; i++) {
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nsec <<= 8;
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nsec |= buf[2 - i];
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}
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sec = buf[9];
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for (i = 0; i < 5; i++) {
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sec <<= 8;
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sec |= buf[8 - i];
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}
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ts->tv_sec = sec;
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ts->tv_nsec = nsec;
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}
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static void idt82p33_timespec_to_byte_array(struct timespec64 const *ts,
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u8 buf[TOD_BYTE_COUNT])
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{
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time64_t sec;
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s32 nsec;
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u8 i;
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nsec = ts->tv_nsec;
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sec = ts->tv_sec;
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for (i = 0; i < 4; i++) {
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buf[i] = nsec & 0xff;
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nsec >>= 8;
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}
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for (i = 4; i < TOD_BYTE_COUNT; i++) {
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buf[i] = sec & 0xff;
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sec >>= 8;
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}
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}
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static int idt82p33_xfer(struct idt82p33 *idt82p33,
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unsigned char regaddr,
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unsigned char *buf,
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unsigned int count,
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int write)
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{
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struct i2c_client *client = idt82p33->client;
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struct i2c_msg msg[2];
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int cnt;
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msg[0].addr = client->addr;
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msg[0].flags = 0;
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msg[0].len = 1;
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msg[0].buf = ®addr;
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msg[1].addr = client->addr;
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msg[1].flags = write ? 0 : I2C_M_RD;
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msg[1].len = count;
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msg[1].buf = buf;
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cnt = i2c_transfer(client->adapter, msg, 2);
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if (cnt < 0) {
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dev_err(&client->dev, "i2c_transfer returned %d\n", cnt);
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return cnt;
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} else if (cnt != 2) {
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dev_err(&client->dev,
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"i2c_transfer sent only %d of %d messages\n", cnt, 2);
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return -EIO;
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}
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return 0;
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}
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static int idt82p33_page_offset(struct idt82p33 *idt82p33, unsigned char val)
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{
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int err;
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if (idt82p33->page_offset == val)
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return 0;
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err = idt82p33_xfer(idt82p33, PAGE_ADDR, &val, sizeof(val), 1);
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if (err)
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dev_err(&idt82p33->client->dev,
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"failed to set page offset %d\n", val);
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else
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idt82p33->page_offset = val;
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return err;
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}
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static int idt82p33_rdwr(struct idt82p33 *idt82p33, unsigned int regaddr,
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unsigned char *buf, unsigned int count, bool write)
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{
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u8 offset, page;
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int err;
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page = _PAGE(regaddr);
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offset = _OFFSET(regaddr);
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err = idt82p33_page_offset(idt82p33, page);
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if (err)
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goto out;
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err = idt82p33_xfer(idt82p33, offset, buf, count, write);
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out:
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return err;
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}
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static int idt82p33_read(struct idt82p33 *idt82p33, unsigned int regaddr,
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unsigned char *buf, unsigned int count)
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{
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return idt82p33_rdwr(idt82p33, regaddr, buf, count, false);
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}
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static int idt82p33_write(struct idt82p33 *idt82p33, unsigned int regaddr,
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unsigned char *buf, unsigned int count)
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{
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return idt82p33_rdwr(idt82p33, regaddr, buf, count, true);
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}
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static int idt82p33_dpll_set_mode(struct idt82p33_channel *channel,
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enum pll_mode mode)
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{
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struct idt82p33 *idt82p33 = channel->idt82p33;
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u8 dpll_mode;
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int err;
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if (channel->pll_mode == mode)
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return 0;
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err = idt82p33_read(idt82p33, channel->dpll_mode_cnfg,
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&dpll_mode, sizeof(dpll_mode));
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if (err)
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return err;
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dpll_mode &= ~(PLL_MODE_MASK << PLL_MODE_SHIFT);
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dpll_mode |= (mode << PLL_MODE_SHIFT);
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err = idt82p33_write(idt82p33, channel->dpll_mode_cnfg,
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&dpll_mode, sizeof(dpll_mode));
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if (err)
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return err;
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channel->pll_mode = dpll_mode;
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return 0;
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}
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static int _idt82p33_gettime(struct idt82p33_channel *channel,
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struct timespec64 *ts)
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{
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struct idt82p33 *idt82p33 = channel->idt82p33;
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u8 buf[TOD_BYTE_COUNT];
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u8 trigger;
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int err;
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trigger = TOD_TRIGGER(HW_TOD_WR_TRIG_SEL_MSB_TOD_CNFG,
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HW_TOD_RD_TRIG_SEL_LSB_TOD_STS);
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err = idt82p33_write(idt82p33, channel->dpll_tod_trigger,
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&trigger, sizeof(trigger));
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if (err)
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return err;
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if (idt82p33->calculate_overhead_flag)
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idt82p33->start_time = ktime_get_raw();
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err = idt82p33_read(idt82p33, channel->dpll_tod_sts, buf, sizeof(buf));
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if (err)
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return err;
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idt82p33_byte_array_to_timespec(ts, buf);
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return 0;
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}
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/*
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* TOD Trigger:
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* Bits[7:4] Write 0x9, MSB write
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* Bits[3:0] Read 0x9, LSB read
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*/
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static int _idt82p33_settime(struct idt82p33_channel *channel,
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struct timespec64 const *ts)
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{
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struct idt82p33 *idt82p33 = channel->idt82p33;
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struct timespec64 local_ts = *ts;
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char buf[TOD_BYTE_COUNT];
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s64 dynamic_overhead_ns;
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unsigned char trigger;
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int err;
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u8 i;
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trigger = TOD_TRIGGER(HW_TOD_WR_TRIG_SEL_MSB_TOD_CNFG,
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HW_TOD_RD_TRIG_SEL_LSB_TOD_STS);
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err = idt82p33_write(idt82p33, channel->dpll_tod_trigger,
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&trigger, sizeof(trigger));
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if (err)
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return err;
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if (idt82p33->calculate_overhead_flag) {
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dynamic_overhead_ns = ktime_to_ns(ktime_get_raw())
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- ktime_to_ns(idt82p33->start_time);
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timespec64_add_ns(&local_ts, dynamic_overhead_ns);
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idt82p33->calculate_overhead_flag = 0;
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}
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idt82p33_timespec_to_byte_array(&local_ts, buf);
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/*
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* Store the new time value.
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*/
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for (i = 0; i < TOD_BYTE_COUNT; i++) {
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err = idt82p33_write(idt82p33, channel->dpll_tod_cnfg + i,
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&buf[i], sizeof(buf[i]));
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if (err)
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return err;
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}
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return err;
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}
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static int _idt82p33_adjtime(struct idt82p33_channel *channel, s64 delta_ns)
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{
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struct idt82p33 *idt82p33 = channel->idt82p33;
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struct timespec64 ts;
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s64 now_ns;
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int err;
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idt82p33->calculate_overhead_flag = 1;
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err = _idt82p33_gettime(channel, &ts);
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if (err)
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return err;
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now_ns = timespec64_to_ns(&ts);
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now_ns += delta_ns + idt82p33->tod_write_overhead_ns;
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ts = ns_to_timespec64(now_ns);
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err = _idt82p33_settime(channel, &ts);
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return err;
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}
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static int _idt82p33_adjfine(struct idt82p33_channel *channel, long scaled_ppm)
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{
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struct idt82p33 *idt82p33 = channel->idt82p33;
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unsigned char buf[5] = {0};
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int neg_adj = 0;
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int err, i;
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s64 fcw;
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if (scaled_ppm == channel->current_freq_ppb)
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return 0;
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/*
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* Frequency Control Word unit is: 1.68 * 10^-10 ppm
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*
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* adjfreq:
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* ppb * 10^9
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* FCW = ----------
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* 168
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*
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* adjfine:
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* scaled_ppm * 5^12
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* FCW = -------------
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* 168 * 2^4
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*/
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if (scaled_ppm < 0) {
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neg_adj = 1;
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scaled_ppm = -scaled_ppm;
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}
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fcw = scaled_ppm * 244140625ULL;
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fcw = div_u64(fcw, 2688);
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if (neg_adj)
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fcw = -fcw;
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for (i = 0; i < 5; i++) {
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buf[i] = fcw & 0xff;
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fcw >>= 8;
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}
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err = idt82p33_dpll_set_mode(channel, PLL_MODE_DCO);
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if (err)
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return err;
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err = idt82p33_write(idt82p33, channel->dpll_freq_cnfg,
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buf, sizeof(buf));
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if (err == 0)
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channel->current_freq_ppb = scaled_ppm;
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return err;
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}
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static int idt82p33_measure_one_byte_write_overhead(
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struct idt82p33_channel *channel, s64 *overhead_ns)
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{
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struct idt82p33 *idt82p33 = channel->idt82p33;
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ktime_t start, stop;
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s64 total_ns;
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u8 trigger;
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int err;
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u8 i;
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total_ns = 0;
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*overhead_ns = 0;
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trigger = TOD_TRIGGER(HW_TOD_WR_TRIG_SEL_MSB_TOD_CNFG,
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HW_TOD_RD_TRIG_SEL_LSB_TOD_STS);
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for (i = 0; i < MAX_MEASURMENT_COUNT; i++) {
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start = ktime_get_raw();
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err = idt82p33_write(idt82p33, channel->dpll_tod_trigger,
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&trigger, sizeof(trigger));
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stop = ktime_get_raw();
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if (err)
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return err;
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total_ns += ktime_to_ns(stop) - ktime_to_ns(start);
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}
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*overhead_ns = div_s64(total_ns, MAX_MEASURMENT_COUNT);
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return err;
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}
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static int idt82p33_measure_tod_write_9_byte_overhead(
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struct idt82p33_channel *channel)
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{
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struct idt82p33 *idt82p33 = channel->idt82p33;
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u8 buf[TOD_BYTE_COUNT];
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ktime_t start, stop;
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s64 total_ns;
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int err = 0;
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u8 i, j;
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total_ns = 0;
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idt82p33->tod_write_overhead_ns = 0;
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for (i = 0; i < MAX_MEASURMENT_COUNT; i++) {
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start = ktime_get_raw();
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/* Need one less byte for applicable overhead */
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for (j = 0; j < (TOD_BYTE_COUNT - 1); j++) {
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err = idt82p33_write(idt82p33,
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channel->dpll_tod_cnfg + i,
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&buf[i], sizeof(buf[i]));
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if (err)
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return err;
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}
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stop = ktime_get_raw();
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total_ns += ktime_to_ns(stop) - ktime_to_ns(start);
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}
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idt82p33->tod_write_overhead_ns = div_s64(total_ns,
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MAX_MEASURMENT_COUNT);
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return err;
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}
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static int idt82p33_measure_settime_gettime_gap_overhead(
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struct idt82p33_channel *channel, s64 *overhead_ns)
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{
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struct timespec64 ts1 = {0, 0};
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struct timespec64 ts2;
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int err;
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*overhead_ns = 0;
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err = _idt82p33_settime(channel, &ts1);
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if (err)
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return err;
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err = _idt82p33_gettime(channel, &ts2);
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if (!err)
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*overhead_ns = timespec64_to_ns(&ts2) - timespec64_to_ns(&ts1);
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return err;
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}
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static int idt82p33_measure_tod_write_overhead(struct idt82p33_channel *channel)
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{
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s64 trailing_overhead_ns, one_byte_write_ns, gap_ns;
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struct idt82p33 *idt82p33 = channel->idt82p33;
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int err;
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idt82p33->tod_write_overhead_ns = 0;
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err = idt82p33_measure_settime_gettime_gap_overhead(channel, &gap_ns);
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if (err)
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return err;
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err = idt82p33_measure_one_byte_write_overhead(channel,
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&one_byte_write_ns);
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if (err)
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return err;
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err = idt82p33_measure_tod_write_9_byte_overhead(channel);
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if (err)
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return err;
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trailing_overhead_ns = gap_ns - (2 * one_byte_write_ns);
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idt82p33->tod_write_overhead_ns -= trailing_overhead_ns;
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return err;
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}
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static int idt82p33_check_and_set_masks(struct idt82p33 *idt82p33,
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u8 page,
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u8 offset,
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u8 val)
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{
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int err = 0;
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if (page == PLLMASK_ADDR_HI && offset == PLLMASK_ADDR_LO) {
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if ((val & 0xfc) || !(val & 0x3)) {
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dev_err(&idt82p33->client->dev,
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"Invalid PLL mask 0x%hhx\n", val);
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err = -EINVAL;
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} else {
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idt82p33->pll_mask = val;
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}
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} else if (page == PLL0_OUTMASK_ADDR_HI &&
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offset == PLL0_OUTMASK_ADDR_LO) {
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idt82p33->channel[0].output_mask = val;
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} else if (page == PLL1_OUTMASK_ADDR_HI &&
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offset == PLL1_OUTMASK_ADDR_LO) {
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idt82p33->channel[1].output_mask = val;
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}
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return err;
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}
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static void idt82p33_display_masks(struct idt82p33 *idt82p33)
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{
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u8 mask, i;
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dev_info(&idt82p33->client->dev,
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"pllmask = 0x%02x\n", idt82p33->pll_mask);
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for (i = 0; i < MAX_PHC_PLL; i++) {
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mask = 1 << i;
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if (mask & idt82p33->pll_mask)
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dev_info(&idt82p33->client->dev,
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"PLL%d output_mask = 0x%04x\n",
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i, idt82p33->channel[i].output_mask);
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}
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}
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static int idt82p33_sync_tod(struct idt82p33_channel *channel, bool enable)
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{
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struct idt82p33 *idt82p33 = channel->idt82p33;
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u8 sync_cnfg;
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int err;
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if (enable == channel->sync_tod_on) {
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if (enable && sync_tod_timeout) {
|
|
mod_delayed_work(system_wq, &channel->sync_tod_work,
|
|
sync_tod_timeout * HZ);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
err = idt82p33_read(idt82p33, channel->dpll_sync_cnfg,
|
|
&sync_cnfg, sizeof(sync_cnfg));
|
|
if (err)
|
|
return err;
|
|
|
|
sync_cnfg &= ~SYNC_TOD;
|
|
|
|
if (enable)
|
|
sync_cnfg |= SYNC_TOD;
|
|
|
|
err = idt82p33_write(idt82p33, channel->dpll_sync_cnfg,
|
|
&sync_cnfg, sizeof(sync_cnfg));
|
|
if (err)
|
|
return err;
|
|
|
|
channel->sync_tod_on = enable;
|
|
|
|
if (enable && sync_tod_timeout) {
|
|
mod_delayed_work(system_wq, &channel->sync_tod_work,
|
|
sync_tod_timeout * HZ);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void idt82p33_sync_tod_work_handler(struct work_struct *work)
|
|
{
|
|
struct idt82p33_channel *channel =
|
|
container_of(work, struct idt82p33_channel, sync_tod_work.work);
|
|
struct idt82p33 *idt82p33 = channel->idt82p33;
|
|
|
|
mutex_lock(&idt82p33->reg_lock);
|
|
|
|
(void)idt82p33_sync_tod(channel, false);
|
|
|
|
mutex_unlock(&idt82p33->reg_lock);
|
|
}
|
|
|
|
static int idt82p33_pps_enable(struct idt82p33_channel *channel, bool enable)
|
|
{
|
|
struct idt82p33 *idt82p33 = channel->idt82p33;
|
|
u8 mask, outn, val;
|
|
int err;
|
|
|
|
mask = channel->output_mask;
|
|
outn = 0;
|
|
|
|
while (mask) {
|
|
if (mask & 0x1) {
|
|
err = idt82p33_read(idt82p33, OUT_MUX_CNFG(outn),
|
|
&val, sizeof(val));
|
|
if (err)
|
|
return err;
|
|
|
|
if (enable)
|
|
val &= ~SQUELCH_ENABLE;
|
|
else
|
|
val |= SQUELCH_ENABLE;
|
|
|
|
err = idt82p33_write(idt82p33, OUT_MUX_CNFG(outn),
|
|
&val, sizeof(val));
|
|
|
|
if (err)
|
|
return err;
|
|
}
|
|
mask >>= 0x1;
|
|
outn++;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int idt82p33_enable_tod(struct idt82p33_channel *channel)
|
|
{
|
|
struct idt82p33 *idt82p33 = channel->idt82p33;
|
|
struct timespec64 ts = {0, 0};
|
|
int err;
|
|
u8 val;
|
|
|
|
val = 0;
|
|
err = idt82p33_write(idt82p33, channel->dpll_input_mode_cnfg,
|
|
&val, sizeof(val));
|
|
if (err)
|
|
return err;
|
|
|
|
err = idt82p33_pps_enable(channel, false);
|
|
|
|
if (err)
|
|
return err;
|
|
|
|
err = idt82p33_measure_tod_write_overhead(channel);
|
|
|
|
if (err)
|
|
return err;
|
|
|
|
err = _idt82p33_settime(channel, &ts);
|
|
|
|
if (err)
|
|
return err;
|
|
|
|
return idt82p33_sync_tod(channel, true);
|
|
}
|
|
|
|
static void idt82p33_ptp_clock_unregister_all(struct idt82p33 *idt82p33)
|
|
{
|
|
struct idt82p33_channel *channel;
|
|
u8 i;
|
|
|
|
for (i = 0; i < MAX_PHC_PLL; i++) {
|
|
|
|
channel = &idt82p33->channel[i];
|
|
|
|
if (channel->ptp_clock) {
|
|
ptp_clock_unregister(channel->ptp_clock);
|
|
cancel_delayed_work_sync(&channel->sync_tod_work);
|
|
}
|
|
}
|
|
}
|
|
|
|
static int idt82p33_enable(struct ptp_clock_info *ptp,
|
|
struct ptp_clock_request *rq, int on)
|
|
{
|
|
struct idt82p33_channel *channel =
|
|
container_of(ptp, struct idt82p33_channel, caps);
|
|
struct idt82p33 *idt82p33 = channel->idt82p33;
|
|
int err;
|
|
|
|
err = -EOPNOTSUPP;
|
|
|
|
mutex_lock(&idt82p33->reg_lock);
|
|
|
|
if (rq->type == PTP_CLK_REQ_PEROUT) {
|
|
if (!on)
|
|
err = idt82p33_pps_enable(channel, false);
|
|
|
|
/* Only accept a 1-PPS aligned to the second. */
|
|
else if (rq->perout.start.nsec || rq->perout.period.sec != 1 ||
|
|
rq->perout.period.nsec) {
|
|
err = -ERANGE;
|
|
} else
|
|
err = idt82p33_pps_enable(channel, true);
|
|
}
|
|
|
|
mutex_unlock(&idt82p33->reg_lock);
|
|
|
|
return err;
|
|
}
|
|
|
|
static int idt82p33_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
|
|
{
|
|
struct idt82p33_channel *channel =
|
|
container_of(ptp, struct idt82p33_channel, caps);
|
|
struct idt82p33 *idt82p33 = channel->idt82p33;
|
|
int err;
|
|
|
|
mutex_lock(&idt82p33->reg_lock);
|
|
err = _idt82p33_adjfine(channel, scaled_ppm);
|
|
mutex_unlock(&idt82p33->reg_lock);
|
|
|
|
return err;
|
|
}
|
|
|
|
static int idt82p33_adjtime(struct ptp_clock_info *ptp, s64 delta_ns)
|
|
{
|
|
struct idt82p33_channel *channel =
|
|
container_of(ptp, struct idt82p33_channel, caps);
|
|
struct idt82p33 *idt82p33 = channel->idt82p33;
|
|
int err;
|
|
|
|
mutex_lock(&idt82p33->reg_lock);
|
|
|
|
if (abs(delta_ns) < phase_snap_threshold) {
|
|
mutex_unlock(&idt82p33->reg_lock);
|
|
return 0;
|
|
}
|
|
|
|
err = _idt82p33_adjtime(channel, delta_ns);
|
|
|
|
if (err) {
|
|
mutex_unlock(&idt82p33->reg_lock);
|
|
return err;
|
|
}
|
|
|
|
err = idt82p33_sync_tod(channel, true);
|
|
|
|
mutex_unlock(&idt82p33->reg_lock);
|
|
|
|
return err;
|
|
}
|
|
|
|
static int idt82p33_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
|
|
{
|
|
struct idt82p33_channel *channel =
|
|
container_of(ptp, struct idt82p33_channel, caps);
|
|
struct idt82p33 *idt82p33 = channel->idt82p33;
|
|
int err;
|
|
|
|
mutex_lock(&idt82p33->reg_lock);
|
|
err = _idt82p33_gettime(channel, ts);
|
|
mutex_unlock(&idt82p33->reg_lock);
|
|
|
|
return err;
|
|
}
|
|
|
|
static int idt82p33_settime(struct ptp_clock_info *ptp,
|
|
const struct timespec64 *ts)
|
|
{
|
|
struct idt82p33_channel *channel =
|
|
container_of(ptp, struct idt82p33_channel, caps);
|
|
struct idt82p33 *idt82p33 = channel->idt82p33;
|
|
int err;
|
|
|
|
mutex_lock(&idt82p33->reg_lock);
|
|
err = _idt82p33_settime(channel, ts);
|
|
mutex_unlock(&idt82p33->reg_lock);
|
|
|
|
return err;
|
|
}
|
|
|
|
static int idt82p33_channel_init(struct idt82p33_channel *channel, int index)
|
|
{
|
|
switch (index) {
|
|
case 0:
|
|
channel->dpll_tod_cnfg = DPLL1_TOD_CNFG;
|
|
channel->dpll_tod_trigger = DPLL1_TOD_TRIGGER;
|
|
channel->dpll_tod_sts = DPLL1_TOD_STS;
|
|
channel->dpll_mode_cnfg = DPLL1_OPERATING_MODE_CNFG;
|
|
channel->dpll_freq_cnfg = DPLL1_HOLDOVER_FREQ_CNFG;
|
|
channel->dpll_phase_cnfg = DPLL1_PHASE_OFFSET_CNFG;
|
|
channel->dpll_sync_cnfg = DPLL1_SYNC_EDGE_CNFG;
|
|
channel->dpll_input_mode_cnfg = DPLL1_INPUT_MODE_CNFG;
|
|
break;
|
|
case 1:
|
|
channel->dpll_tod_cnfg = DPLL2_TOD_CNFG;
|
|
channel->dpll_tod_trigger = DPLL2_TOD_TRIGGER;
|
|
channel->dpll_tod_sts = DPLL2_TOD_STS;
|
|
channel->dpll_mode_cnfg = DPLL2_OPERATING_MODE_CNFG;
|
|
channel->dpll_freq_cnfg = DPLL2_HOLDOVER_FREQ_CNFG;
|
|
channel->dpll_phase_cnfg = DPLL2_PHASE_OFFSET_CNFG;
|
|
channel->dpll_sync_cnfg = DPLL2_SYNC_EDGE_CNFG;
|
|
channel->dpll_input_mode_cnfg = DPLL2_INPUT_MODE_CNFG;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
INIT_DELAYED_WORK(&channel->sync_tod_work,
|
|
idt82p33_sync_tod_work_handler);
|
|
channel->sync_tod_on = false;
|
|
channel->current_freq_ppb = 0;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void idt82p33_caps_init(struct ptp_clock_info *caps)
|
|
{
|
|
caps->owner = THIS_MODULE;
|
|
caps->max_adj = 92000;
|
|
caps->adjfine = idt82p33_adjfine;
|
|
caps->adjtime = idt82p33_adjtime;
|
|
caps->gettime64 = idt82p33_gettime;
|
|
caps->settime64 = idt82p33_settime;
|
|
caps->enable = idt82p33_enable;
|
|
}
|
|
|
|
static int idt82p33_enable_channel(struct idt82p33 *idt82p33, u32 index)
|
|
{
|
|
struct idt82p33_channel *channel;
|
|
int err;
|
|
|
|
if (!(index < MAX_PHC_PLL))
|
|
return -EINVAL;
|
|
|
|
channel = &idt82p33->channel[index];
|
|
|
|
err = idt82p33_channel_init(channel, index);
|
|
if (err)
|
|
return err;
|
|
|
|
channel->idt82p33 = idt82p33;
|
|
|
|
idt82p33_caps_init(&channel->caps);
|
|
snprintf(channel->caps.name, sizeof(channel->caps.name),
|
|
"IDT 82P33 PLL%u", index);
|
|
channel->caps.n_per_out = hweight8(channel->output_mask);
|
|
|
|
err = idt82p33_dpll_set_mode(channel, PLL_MODE_DCO);
|
|
if (err)
|
|
return err;
|
|
|
|
err = idt82p33_enable_tod(channel);
|
|
if (err)
|
|
return err;
|
|
|
|
channel->ptp_clock = ptp_clock_register(&channel->caps, NULL);
|
|
|
|
if (IS_ERR(channel->ptp_clock)) {
|
|
err = PTR_ERR(channel->ptp_clock);
|
|
channel->ptp_clock = NULL;
|
|
return err;
|
|
}
|
|
|
|
if (!channel->ptp_clock)
|
|
return -ENOTSUPP;
|
|
|
|
dev_info(&idt82p33->client->dev, "PLL%d registered as ptp%d\n",
|
|
index, channel->ptp_clock->index);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int idt82p33_load_firmware(struct idt82p33 *idt82p33)
|
|
{
|
|
const struct firmware *fw;
|
|
struct idt82p33_fwrc *rec;
|
|
u8 loaddr, page, val;
|
|
int err;
|
|
s32 len;
|
|
|
|
dev_dbg(&idt82p33->client->dev,
|
|
"requesting firmware '%s'\n", FW_FILENAME);
|
|
|
|
err = request_firmware(&fw, FW_FILENAME, &idt82p33->client->dev);
|
|
|
|
if (err)
|
|
return err;
|
|
|
|
dev_dbg(&idt82p33->client->dev, "firmware size %zu bytes\n", fw->size);
|
|
|
|
rec = (struct idt82p33_fwrc *) fw->data;
|
|
|
|
for (len = fw->size; len > 0; len -= sizeof(*rec)) {
|
|
|
|
if (rec->reserved) {
|
|
dev_err(&idt82p33->client->dev,
|
|
"bad firmware, reserved field non-zero\n");
|
|
err = -EINVAL;
|
|
} else {
|
|
val = rec->value;
|
|
loaddr = rec->loaddr;
|
|
page = rec->hiaddr;
|
|
|
|
rec++;
|
|
|
|
err = idt82p33_check_and_set_masks(idt82p33, page,
|
|
loaddr, val);
|
|
}
|
|
|
|
if (err == 0) {
|
|
/* maximum 8 pages */
|
|
if (page >= PAGE_NUM)
|
|
continue;
|
|
|
|
/* Page size 128, last 4 bytes of page skipped */
|
|
if (((loaddr > 0x7b) && (loaddr <= 0x7f))
|
|
|| loaddr > 0xfb)
|
|
continue;
|
|
|
|
err = idt82p33_write(idt82p33, _ADDR(page, loaddr),
|
|
&val, sizeof(val));
|
|
}
|
|
|
|
if (err)
|
|
goto out;
|
|
}
|
|
|
|
idt82p33_display_masks(idt82p33);
|
|
out:
|
|
release_firmware(fw);
|
|
return err;
|
|
}
|
|
|
|
|
|
static int idt82p33_probe(struct i2c_client *client,
|
|
const struct i2c_device_id *id)
|
|
{
|
|
struct idt82p33 *idt82p33;
|
|
int err;
|
|
u8 i;
|
|
|
|
(void)id;
|
|
|
|
idt82p33 = devm_kzalloc(&client->dev,
|
|
sizeof(struct idt82p33), GFP_KERNEL);
|
|
if (!idt82p33)
|
|
return -ENOMEM;
|
|
|
|
mutex_init(&idt82p33->reg_lock);
|
|
|
|
idt82p33->client = client;
|
|
idt82p33->page_offset = 0xff;
|
|
idt82p33->tod_write_overhead_ns = 0;
|
|
idt82p33->calculate_overhead_flag = 0;
|
|
idt82p33->pll_mask = DEFAULT_PLL_MASK;
|
|
idt82p33->channel[0].output_mask = DEFAULT_OUTPUT_MASK_PLL0;
|
|
idt82p33->channel[1].output_mask = DEFAULT_OUTPUT_MASK_PLL1;
|
|
|
|
mutex_lock(&idt82p33->reg_lock);
|
|
|
|
err = idt82p33_load_firmware(idt82p33);
|
|
|
|
if (err)
|
|
dev_warn(&idt82p33->client->dev,
|
|
"loading firmware failed with %d\n", err);
|
|
|
|
if (idt82p33->pll_mask) {
|
|
for (i = 0; i < MAX_PHC_PLL; i++) {
|
|
if (idt82p33->pll_mask & (1 << i)) {
|
|
err = idt82p33_enable_channel(idt82p33, i);
|
|
if (err)
|
|
break;
|
|
}
|
|
}
|
|
} else {
|
|
dev_err(&idt82p33->client->dev,
|
|
"no PLLs flagged as PHCs, nothing to do\n");
|
|
err = -ENODEV;
|
|
}
|
|
|
|
mutex_unlock(&idt82p33->reg_lock);
|
|
|
|
if (err) {
|
|
idt82p33_ptp_clock_unregister_all(idt82p33);
|
|
return err;
|
|
}
|
|
|
|
i2c_set_clientdata(client, idt82p33);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int idt82p33_remove(struct i2c_client *client)
|
|
{
|
|
struct idt82p33 *idt82p33 = i2c_get_clientdata(client);
|
|
|
|
idt82p33_ptp_clock_unregister_all(idt82p33);
|
|
mutex_destroy(&idt82p33->reg_lock);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_OF
|
|
static const struct of_device_id idt82p33_dt_id[] = {
|
|
{ .compatible = "idt,82p33810" },
|
|
{ .compatible = "idt,82p33813" },
|
|
{ .compatible = "idt,82p33814" },
|
|
{ .compatible = "idt,82p33831" },
|
|
{ .compatible = "idt,82p33910" },
|
|
{ .compatible = "idt,82p33913" },
|
|
{ .compatible = "idt,82p33914" },
|
|
{ .compatible = "idt,82p33931" },
|
|
{},
|
|
};
|
|
MODULE_DEVICE_TABLE(of, idt82p33_dt_id);
|
|
#endif
|
|
|
|
static const struct i2c_device_id idt82p33_i2c_id[] = {
|
|
{ "idt82p33810", },
|
|
{ "idt82p33813", },
|
|
{ "idt82p33814", },
|
|
{ "idt82p33831", },
|
|
{ "idt82p33910", },
|
|
{ "idt82p33913", },
|
|
{ "idt82p33914", },
|
|
{ "idt82p33931", },
|
|
{},
|
|
};
|
|
MODULE_DEVICE_TABLE(i2c, idt82p33_i2c_id);
|
|
|
|
static struct i2c_driver idt82p33_driver = {
|
|
.driver = {
|
|
.of_match_table = of_match_ptr(idt82p33_dt_id),
|
|
.name = "idt82p33",
|
|
},
|
|
.probe = idt82p33_probe,
|
|
.remove = idt82p33_remove,
|
|
.id_table = idt82p33_i2c_id,
|
|
};
|
|
|
|
module_i2c_driver(idt82p33_driver);
|