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ddd5ed3a90
None of the existing platforms connect the R/B pin to a GPIO (they all use one of the dedicated R/B pin). Anyway, if we ever get short of native R/B pins, it's probably better to fallback to STATUS reg polling than trying to poll a GPIO. Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com> Reviewed-by: Rob Herring <robh@kernel.org>
49 lines
1.4 KiB
Plaintext
49 lines
1.4 KiB
Plaintext
Allwinner NAND Flash Controller (NFC)
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Required properties:
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- compatible : "allwinner,sun4i-a10-nand".
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- reg : shall contain registers location and length for data and reg.
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- interrupts : shall define the nand controller interrupt.
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- #address-cells: shall be set to 1. Encode the nand CS.
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- #size-cells : shall be set to 0.
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- clocks : shall reference nand controller clocks.
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- clock-names : nand controller internal clock names. Shall contain :
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* "ahb" : AHB gating clock
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* "mod" : nand controller clock
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Optional properties:
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- dmas : shall reference DMA channel associated to the NAND controller.
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- dma-names : shall be "rxtx".
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Optional children nodes:
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Children nodes represent the available nand chips.
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Optional properties:
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- reset : phandle + reset specifier pair
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- reset-names : must contain "ahb"
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- allwinner,rb : shall contain the native Ready/Busy ids.
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- nand-ecc-mode : one of the supported ECC modes ("hw", "soft", "soft_bch" or
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"none")
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see Documentation/devicetree/bindings/mtd/nand.txt for generic bindings.
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Examples:
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nfc: nand@1c03000 {
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compatible = "allwinner,sun4i-a10-nand";
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reg = <0x01c03000 0x1000>;
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interrupts = <0 37 1>;
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clocks = <&ahb_gates 13>, <&nand_clk>;
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clock-names = "ahb", "mod";
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&nand_pins_a &nand_cs0_pins_a &nand_rb0_pins_a>;
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nand@0 {
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reg = <0>;
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allwinner,rb = <0>;
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nand-ecc-mode = "soft_bch";
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};
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};
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