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Document Synopsys DesignWare I3C master module Signed-off-by: Vitor Soares <vitor.soares@synopsys.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
42 lines
1.1 KiB
Plaintext
42 lines
1.1 KiB
Plaintext
Bindings for Synopsys DesignWare I3C master block
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=================================================
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Required properties:
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--------------------
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- compatible: shall be "snps,dw-i3c-master-1.00a"
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- clocks: shall reference the core_clk
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- interrupts: the interrupt line connected to this I3C master
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- reg: Offset and length of I3C master registers
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Mandatory properties defined by the generic binding (see
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Documentation/devicetree/bindings/i3c/i3c.txt for more details):
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- #address-cells: shall be set to 3
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- #size-cells: shall be set to 0
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Optional properties defined by the generic binding (see
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Documentation/devicetree/bindings/i3c/i3c.txt for more details):
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- i2c-scl-hz
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- i3c-scl-hz
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I3C device connected on the bus follow the generic description (see
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Documentation/devicetree/bindings/i3c/i3c.txt for more details).
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Example:
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i3c-master@2000 {
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compatible = "snps,dw-i3c-master-1.00a";
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#address-cells = <3>;
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#size-cells = <0>;
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reg = <0x02000 0x1000>;
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interrupts = <0>;
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clocks = <&i3cclk>;
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eeprom@57{
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compatible = "atmel,24c01";
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reg = <0x57 0x0 0x10>;
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pagesize = <0x8>;
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};
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};
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