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80c226fbef
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/linux-m68k: m68k: Add missing I/O macros {in,out}{w,l}_p() for !CONFIG_ISA m68k: Remove big kernel lock in cache flush code m68k: __pa(): cast arg to long fbdev: atafb - Remove undead ifdef ATAFB_FALCON zorro: Fix device_register() error handling fbdev/m68k: Fix section mismatches in q40fb.c m68k/m68knommu: merge the MMU and non-MMU traps.h m68k/m68knommu: merge MMU and non-MMU thread_info.h m68k/m68knommu: merge MMU and non-MMU atomic.h m68k/m68knommu: clean up page.h m68k/m68knommu: merge machdep.h files into a single file m68k/m68knommu: merge MMU and non-MMU string.h m68k/m68knommu: Remove dead SMP config option m68k: move definition of THREAD_SIZE into thread_info_mm.h m68k: Use asm-generic/ioctls.h (enables termiox) m68k: Remove dead GG2 config option
154 lines
4.1 KiB
C
154 lines
4.1 KiB
C
#ifndef _M68KNOMMU_SYSTEM_H
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#define _M68KNOMMU_SYSTEM_H
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#include <linux/linkage.h>
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#include <linux/irqflags.h>
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#include <asm/segment.h>
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#include <asm/entry.h>
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/*
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* switch_to(n) should switch tasks to task ptr, first checking that
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* ptr isn't the current task, in which case it does nothing. This
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* also clears the TS-flag if the task we switched to has used the
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* math co-processor latest.
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*/
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/*
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* switch_to() saves the extra registers, that are not saved
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* automatically by SAVE_SWITCH_STACK in resume(), ie. d0-d5 and
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* a0-a1. Some of these are used by schedule() and its predecessors
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* and so we might get see unexpected behaviors when a task returns
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* with unexpected register values.
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*
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* syscall stores these registers itself and none of them are used
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* by syscall after the function in the syscall has been called.
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*
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* Beware that resume now expects *next to be in d1 and the offset of
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* tss to be in a1. This saves a few instructions as we no longer have
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* to push them onto the stack and read them back right after.
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*
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* 02/17/96 - Jes Sorensen (jds@kom.auc.dk)
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*
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* Changed 96/09/19 by Andreas Schwab
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* pass prev in a0, next in a1, offset of tss in d1, and whether
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* the mm structures are shared in d2 (to avoid atc flushing).
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*/
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asmlinkage void resume(void);
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#define switch_to(prev,next,last) \
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{ \
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void *_last; \
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__asm__ __volatile__( \
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"movel %1, %%a0\n\t" \
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"movel %2, %%a1\n\t" \
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"jbsr resume\n\t" \
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"movel %%d1, %0\n\t" \
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: "=d" (_last) \
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: "d" (prev), "d" (next) \
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: "cc", "d0", "d1", "d2", "d3", "d4", "d5", "a0", "a1"); \
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(last) = _last; \
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}
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#define iret() __asm__ __volatile__ ("rte": : :"memory", "sp", "cc")
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/*
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* Force strict CPU ordering.
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* Not really required on m68k...
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*/
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#define nop() asm volatile ("nop"::)
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#define mb() asm volatile ("" : : :"memory")
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#define rmb() asm volatile ("" : : :"memory")
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#define wmb() asm volatile ("" : : :"memory")
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#define set_mb(var, value) ({ (var) = (value); wmb(); })
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#define smp_mb() barrier()
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#define smp_rmb() barrier()
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#define smp_wmb() barrier()
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#define smp_read_barrier_depends() do { } while(0)
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#define read_barrier_depends() ((void)0)
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#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
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struct __xchg_dummy { unsigned long a[100]; };
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#define __xg(x) ((volatile struct __xchg_dummy *)(x))
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#ifndef CONFIG_RMW_INSNS
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static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
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{
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unsigned long tmp, flags;
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local_irq_save(flags);
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switch (size) {
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case 1:
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__asm__ __volatile__
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("moveb %2,%0\n\t"
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"moveb %1,%2"
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: "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
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break;
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case 2:
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__asm__ __volatile__
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("movew %2,%0\n\t"
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"movew %1,%2"
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: "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
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break;
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case 4:
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__asm__ __volatile__
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("movel %2,%0\n\t"
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"movel %1,%2"
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: "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
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break;
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}
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local_irq_restore(flags);
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return tmp;
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}
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#else
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static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
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{
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switch (size) {
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case 1:
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__asm__ __volatile__
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("moveb %2,%0\n\t"
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"1:\n\t"
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"casb %0,%1,%2\n\t"
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"jne 1b"
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: "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory");
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break;
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case 2:
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__asm__ __volatile__
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("movew %2,%0\n\t"
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"1:\n\t"
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"casw %0,%1,%2\n\t"
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"jne 1b"
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: "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory");
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break;
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case 4:
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__asm__ __volatile__
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("movel %2,%0\n\t"
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"1:\n\t"
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"casl %0,%1,%2\n\t"
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"jne 1b"
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: "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory");
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break;
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}
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return x;
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}
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#endif
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#include <asm-generic/cmpxchg-local.h>
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/*
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* cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
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* them available.
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*/
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#define cmpxchg_local(ptr, o, n) \
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((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\
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(unsigned long)(n), sizeof(*(ptr))))
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#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
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#include <asm-generic/cmpxchg.h>
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#define arch_align_stack(x) (x)
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#endif /* _M68KNOMMU_SYSTEM_H */
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