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ec8f7f3342
Switching from TVAL to CVAL has a small drawback: we need an ISB before reading the counter. We cannot get rid of it, but we can instead remove the one that comes just after writing to CVAL. This reduces the number of ISBs from 3 to 2 when programming the timer. Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20211017124225.3018098-12-maz@kernel.org Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
147 lines
3.1 KiB
C
147 lines
3.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __ASMARM_ARCH_TIMER_H
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#define __ASMARM_ARCH_TIMER_H
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#include <asm/barrier.h>
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#include <asm/errno.h>
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#include <asm/hwcap.h>
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#include <linux/clocksource.h>
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#include <linux/init.h>
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#include <linux/io-64-nonatomic-lo-hi.h>
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#include <linux/types.h>
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#include <clocksource/arm_arch_timer.h>
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#ifdef CONFIG_ARM_ARCH_TIMER
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/* 32bit ARM doesn't know anything about timer errata... */
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#define has_erratum_handler(h) (false)
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#define erratum_handler(h) (arch_timer_##h)
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int arch_timer_arch_init(void);
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/*
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* These register accessors are marked inline so the compiler can
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* nicely work out which register we want, and chuck away the rest of
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* the code. At least it does so with a recent GCC (4.6.3).
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*/
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static __always_inline
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void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u64 val)
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{
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if (access == ARCH_TIMER_PHYS_ACCESS) {
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switch (reg) {
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case ARCH_TIMER_REG_CTRL:
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asm volatile("mcr p15, 0, %0, c14, c2, 1" : : "r" ((u32)val));
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isb();
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break;
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case ARCH_TIMER_REG_CVAL:
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asm volatile("mcrr p15, 2, %Q0, %R0, c14" : : "r" (val));
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break;
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default:
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BUILD_BUG();
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}
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} else if (access == ARCH_TIMER_VIRT_ACCESS) {
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switch (reg) {
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case ARCH_TIMER_REG_CTRL:
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asm volatile("mcr p15, 0, %0, c14, c3, 1" : : "r" ((u32)val));
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isb();
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break;
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case ARCH_TIMER_REG_CVAL:
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asm volatile("mcrr p15, 3, %Q0, %R0, c14" : : "r" (val));
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break;
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default:
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BUILD_BUG();
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}
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} else {
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BUILD_BUG();
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}
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}
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static __always_inline
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u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)
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{
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u32 val = 0;
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if (access == ARCH_TIMER_PHYS_ACCESS) {
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switch (reg) {
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case ARCH_TIMER_REG_CTRL:
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asm volatile("mrc p15, 0, %0, c14, c2, 1" : "=r" (val));
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break;
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default:
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BUILD_BUG();
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}
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} else if (access == ARCH_TIMER_VIRT_ACCESS) {
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switch (reg) {
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case ARCH_TIMER_REG_CTRL:
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asm volatile("mrc p15, 0, %0, c14, c3, 1" : "=r" (val));
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break;
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default:
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BUILD_BUG();
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}
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} else {
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BUILD_BUG();
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}
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return val;
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}
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static inline u32 arch_timer_get_cntfrq(void)
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{
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u32 val;
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asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (val));
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return val;
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}
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static inline u64 __arch_counter_get_cntpct(void)
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{
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u64 cval;
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isb();
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asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (cval));
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return cval;
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}
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static inline u64 __arch_counter_get_cntpct_stable(void)
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{
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return __arch_counter_get_cntpct();
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}
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static inline u64 __arch_counter_get_cntvct(void)
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{
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u64 cval;
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isb();
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asm volatile("mrrc p15, 1, %Q0, %R0, c14" : "=r" (cval));
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return cval;
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}
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static inline u64 __arch_counter_get_cntvct_stable(void)
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{
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return __arch_counter_get_cntvct();
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}
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static inline u32 arch_timer_get_cntkctl(void)
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{
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u32 cntkctl;
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asm volatile("mrc p15, 0, %0, c14, c1, 0" : "=r" (cntkctl));
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return cntkctl;
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}
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static inline void arch_timer_set_cntkctl(u32 cntkctl)
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{
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asm volatile("mcr p15, 0, %0, c14, c1, 0" : : "r" (cntkctl));
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isb();
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}
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static inline void arch_timer_set_evtstrm_feature(void)
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{
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elf_hwcap |= HWCAP_EVTSTRM;
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}
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static inline bool arch_timer_have_evtstrm_feature(void)
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{
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return elf_hwcap & HWCAP_EVTSTRM;
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}
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#endif
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#endif
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