Gregory CLEMENT d7f3ec2b69 ARM: mvebu: add CA9 MPcore SoC Controller node ... The CA9 MPcore SoC Control block is a set of registers that allows to configure certain internal aspects of the core blocks of the SoC (Cortex-A9, L2 cache controller, etc.). In most cases, the default values are fine so they aren't many reasons to touch those registers, but there is one exception: to support cpuidle on Armada 38x, we need to modify the value of the CA9 MPcore Reset Control register. Therefore, this commit adds a new Device Tree binding for this hardware block, and uses this new binding for the Armada 38x Device Tree file. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: devicetree@vger.kernel.org Link: https://lkml.kernel.org/r/1404913221-17343-11-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>		2014-07-16 12:34:22 +00:00
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bindings	ARM: mvebu: add CA9 MPcore SoC Controller node	2014-07-16 12:34:22 +00:00
00-INDEX	Documentation/: update 00-INDEX files	2014-02-10 16:01:40 -08:00
booting-without-of.txt	dt/bindings: Remove all references to device_type "ethernet-phy"	2014-01-16 11:11:51 +00:00
usage-model.txt