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Tegra114's AHUB shares a design with Tegra30, with the followin changes: * Supports more (10 vs. 4) bi-directional FIFO channels into RAM. * Requires a separate block of registers to support the above. * Supports more attached clients, i.e. new audio multiplexing and de-multiplexing modules. * Is affected by more clocks due to the above. This change fully defines the device tree binding changes required to represent these changes, and minimally extends the driver to support the new hardware, without exposing any of the new FIFO channels. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
49 lines
2.2 KiB
Plaintext
49 lines
2.2 KiB
Plaintext
NVIDIA Tegra30 AHUB (Audio Hub)
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Required properties:
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- compatible : "nvidia,tegra30-ahub", "nvidia,tegra114-ahub", etc.
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- reg : Should contain the register physical address and length for each of
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the AHUB's register blocks.
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- Tegra30 requires 2 entries, for the APBIF and AHUB/AUDIO register blocks.
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- Tegra114 requires an additional entry, for the APBIF2 register block.
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- interrupts : Should contain AHUB interrupt
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- nvidia,dma-request-selector : A list of the DMA channel specifiers. Each
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entry contains the Tegra DMA controller's phandle and request selector.
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If a single entry is present, the request selectors for the channels are
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assumed to be contiguous, and increment from this value.
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If multiple values are given, one value must be given per channel.
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- clocks : Must contain an entry for each required entry in clock-names.
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- clock-names : Must include the following entries:
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- Tegra30: Requires d_audio, apbif, i2s0, i2s1, i2s2, i2s3, i2s4, dam0,
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dam1, dam2, spdif_in.
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- Tegra114: Additionally requires amx, adx.
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- ranges : The bus address mapping for the configlink register bus.
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Can be empty since the mapping is 1:1.
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- #address-cells : For the configlink bus. Should be <1>;
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- #size-cells : For the configlink bus. Should be <1>.
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AHUB client modules need to specify the IDs of their CIFs (Client InterFaces).
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For RX CIFs, the numbers indicate the register number within AHUB routing
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register space (APBIF 0..3 RX, I2S 0..5 RX, DAM 0..2 RX 0..1, SPDIF RX 0..1).
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For TX CIFs, the numbers indicate the bit position within the AHUB routing
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registers (APBIF 0..3 TX, I2S 0..5 TX, DAM 0..2 TX, SPDIF TX 0..1).
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Example:
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ahub@70080000 {
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compatible = "nvidia,tegra30-ahub";
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reg = <0x70080000 0x200 0x70080200 0x100>;
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interrupts = < 0 103 0x04 >;
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nvidia,dma-request-selector = <&apbdma 1>;
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clocks = <&tegra_car 106>, <&tegra_car 107>, <&tegra_car 30>,
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<&tegra_car 11>, <&tegra_car 18>, <&tegra_car 101>,
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<&tegra_car 102>, <&tegra_car 108>, <&tegra_car 109>,
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<&tegra_car 110>, <&tegra_car 162>;
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clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
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"i2s3", "i2s4", "dam0", "dam1", "dam2",
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"spdif_in";
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ranges;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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