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d6ba745d0a
IFC_FIR_OP_CMD0 issues command for execution without checking flash readiness. It may cause problem if flash is not ready. Instead use IFC_FIR_OP_CW0 which Wait for tWB time and poll R/B to return high or time-out, before issuing command. NAND_CMD_READID command implemention does not fulfill above requirement. So update its programming. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Hemant Nautiyal <hemant.nautiyal@freescale.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
1104 lines
30 KiB
C
1104 lines
30 KiB
C
/*
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* Freescale Integrated Flash Controller NAND driver
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*
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* Copyright 2011-2012 Freescale Semiconductor, Inc
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*
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* Author: Dipen Dudhat <Dipen.Dudhat@freescale.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/partitions.h>
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#include <linux/mtd/nand_ecc.h>
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#include <asm/fsl_ifc.h>
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#define FSL_IFC_V1_1_0 0x01010000
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#define ERR_BYTE 0xFF /* Value returned for read
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bytes when read failed */
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#define IFC_TIMEOUT_MSECS 500 /* Maximum number of mSecs to wait
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for IFC NAND Machine */
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struct fsl_ifc_ctrl;
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/* mtd information per set */
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struct fsl_ifc_mtd {
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struct mtd_info mtd;
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struct nand_chip chip;
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struct fsl_ifc_ctrl *ctrl;
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struct device *dev;
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int bank; /* Chip select bank number */
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unsigned int bufnum_mask; /* bufnum = page & bufnum_mask */
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u8 __iomem *vbase; /* Chip select base virtual address */
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};
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/* overview of the fsl ifc controller */
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struct fsl_ifc_nand_ctrl {
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struct nand_hw_control controller;
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struct fsl_ifc_mtd *chips[FSL_IFC_BANK_COUNT];
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u8 __iomem *addr; /* Address of assigned IFC buffer */
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unsigned int page; /* Last page written to / read from */
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unsigned int read_bytes;/* Number of bytes read during command */
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unsigned int column; /* Saved column from SEQIN */
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unsigned int index; /* Pointer to next byte to 'read' */
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unsigned int oob; /* Non zero if operating on OOB data */
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unsigned int eccread; /* Non zero for a full-page ECC read */
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unsigned int counter; /* counter for the initializations */
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unsigned int max_bitflips; /* Saved during READ0 cmd */
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};
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static struct fsl_ifc_nand_ctrl *ifc_nand_ctrl;
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/* 512-byte page with 4-bit ECC, 8-bit */
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static struct nand_ecclayout oob_512_8bit_ecc4 = {
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.eccbytes = 8,
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.eccpos = {8, 9, 10, 11, 12, 13, 14, 15},
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.oobfree = { {0, 5}, {6, 2} },
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};
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/* 512-byte page with 4-bit ECC, 16-bit */
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static struct nand_ecclayout oob_512_16bit_ecc4 = {
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.eccbytes = 8,
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.eccpos = {8, 9, 10, 11, 12, 13, 14, 15},
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.oobfree = { {2, 6}, },
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};
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/* 2048-byte page size with 4-bit ECC */
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static struct nand_ecclayout oob_2048_ecc4 = {
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.eccbytes = 32,
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.eccpos = {
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8, 9, 10, 11, 12, 13, 14, 15,
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16, 17, 18, 19, 20, 21, 22, 23,
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24, 25, 26, 27, 28, 29, 30, 31,
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32, 33, 34, 35, 36, 37, 38, 39,
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},
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.oobfree = { {2, 6}, {40, 24} },
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};
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/* 4096-byte page size with 4-bit ECC */
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static struct nand_ecclayout oob_4096_ecc4 = {
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.eccbytes = 64,
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.eccpos = {
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8, 9, 10, 11, 12, 13, 14, 15,
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16, 17, 18, 19, 20, 21, 22, 23,
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24, 25, 26, 27, 28, 29, 30, 31,
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32, 33, 34, 35, 36, 37, 38, 39,
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40, 41, 42, 43, 44, 45, 46, 47,
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48, 49, 50, 51, 52, 53, 54, 55,
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56, 57, 58, 59, 60, 61, 62, 63,
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64, 65, 66, 67, 68, 69, 70, 71,
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},
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.oobfree = { {2, 6}, {72, 56} },
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};
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/* 4096-byte page size with 8-bit ECC -- requires 218-byte OOB */
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static struct nand_ecclayout oob_4096_ecc8 = {
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.eccbytes = 128,
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.eccpos = {
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8, 9, 10, 11, 12, 13, 14, 15,
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16, 17, 18, 19, 20, 21, 22, 23,
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24, 25, 26, 27, 28, 29, 30, 31,
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32, 33, 34, 35, 36, 37, 38, 39,
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40, 41, 42, 43, 44, 45, 46, 47,
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48, 49, 50, 51, 52, 53, 54, 55,
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56, 57, 58, 59, 60, 61, 62, 63,
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64, 65, 66, 67, 68, 69, 70, 71,
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72, 73, 74, 75, 76, 77, 78, 79,
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80, 81, 82, 83, 84, 85, 86, 87,
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88, 89, 90, 91, 92, 93, 94, 95,
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96, 97, 98, 99, 100, 101, 102, 103,
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104, 105, 106, 107, 108, 109, 110, 111,
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112, 113, 114, 115, 116, 117, 118, 119,
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120, 121, 122, 123, 124, 125, 126, 127,
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128, 129, 130, 131, 132, 133, 134, 135,
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},
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.oobfree = { {2, 6}, {136, 82} },
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};
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/*
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* Generic flash bbt descriptors
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*/
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static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
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static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
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static struct nand_bbt_descr bbt_main_descr = {
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.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
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NAND_BBT_2BIT | NAND_BBT_VERSION,
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.offs = 2, /* 0 on 8-bit small page */
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.len = 4,
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.veroffs = 6,
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.maxblocks = 4,
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.pattern = bbt_pattern,
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};
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static struct nand_bbt_descr bbt_mirror_descr = {
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.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
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NAND_BBT_2BIT | NAND_BBT_VERSION,
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.offs = 2, /* 0 on 8-bit small page */
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.len = 4,
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.veroffs = 6,
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.maxblocks = 4,
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.pattern = mirror_pattern,
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};
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/*
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* Set up the IFC hardware block and page address fields, and the ifc nand
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* structure addr field to point to the correct IFC buffer in memory
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*/
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static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
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{
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struct nand_chip *chip = mtd->priv;
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struct fsl_ifc_mtd *priv = chip->priv;
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struct fsl_ifc_ctrl *ctrl = priv->ctrl;
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struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
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int buf_num;
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ifc_nand_ctrl->page = page_addr;
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/* Program ROW0/COL0 */
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out_be32(&ifc->ifc_nand.row0, page_addr);
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out_be32(&ifc->ifc_nand.col0, (oob ? IFC_NAND_COL_MS : 0) | column);
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buf_num = page_addr & priv->bufnum_mask;
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ifc_nand_ctrl->addr = priv->vbase + buf_num * (mtd->writesize * 2);
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ifc_nand_ctrl->index = column;
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/* for OOB data point to the second half of the buffer */
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if (oob)
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ifc_nand_ctrl->index += mtd->writesize;
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}
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static int is_blank(struct mtd_info *mtd, unsigned int bufnum)
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{
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struct nand_chip *chip = mtd->priv;
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struct fsl_ifc_mtd *priv = chip->priv;
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u8 __iomem *addr = priv->vbase + bufnum * (mtd->writesize * 2);
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u32 __iomem *mainarea = (u32 __iomem *)addr;
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u8 __iomem *oob = addr + mtd->writesize;
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int i;
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for (i = 0; i < mtd->writesize / 4; i++) {
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if (__raw_readl(&mainarea[i]) != 0xffffffff)
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return 0;
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}
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for (i = 0; i < chip->ecc.layout->eccbytes; i++) {
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int pos = chip->ecc.layout->eccpos[i];
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if (__raw_readb(&oob[pos]) != 0xff)
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return 0;
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}
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return 1;
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}
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/* returns nonzero if entire page is blank */
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static int check_read_ecc(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
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u32 *eccstat, unsigned int bufnum)
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{
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u32 reg = eccstat[bufnum / 4];
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int errors;
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errors = (reg >> ((3 - bufnum % 4) * 8)) & 15;
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return errors;
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}
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/*
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* execute IFC NAND command and wait for it to complete
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*/
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static void fsl_ifc_run_command(struct mtd_info *mtd)
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{
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struct nand_chip *chip = mtd->priv;
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struct fsl_ifc_mtd *priv = chip->priv;
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struct fsl_ifc_ctrl *ctrl = priv->ctrl;
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struct fsl_ifc_nand_ctrl *nctrl = ifc_nand_ctrl;
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struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
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u32 eccstat[4];
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int i;
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/* set the chip select for NAND Transaction */
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out_be32(&ifc->ifc_nand.nand_csel, priv->bank << IFC_NAND_CSEL_SHIFT);
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dev_vdbg(priv->dev,
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"%s: fir0=%08x fcr0=%08x\n",
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__func__,
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in_be32(&ifc->ifc_nand.nand_fir0),
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in_be32(&ifc->ifc_nand.nand_fcr0));
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ctrl->nand_stat = 0;
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/* start read/write seq */
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out_be32(&ifc->ifc_nand.nandseq_strt, IFC_NAND_SEQ_STRT_FIR_STRT);
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/* wait for command complete flag or timeout */
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wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat,
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IFC_TIMEOUT_MSECS * HZ/1000);
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/* ctrl->nand_stat will be updated from IRQ context */
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if (!ctrl->nand_stat)
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dev_err(priv->dev, "Controller is not responding\n");
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if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_FTOER)
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dev_err(priv->dev, "NAND Flash Timeout Error\n");
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if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_WPER)
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dev_err(priv->dev, "NAND Flash Write Protect Error\n");
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nctrl->max_bitflips = 0;
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if (nctrl->eccread) {
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int errors;
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int bufnum = nctrl->page & priv->bufnum_mask;
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int sector = bufnum * chip->ecc.steps;
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int sector_end = sector + chip->ecc.steps - 1;
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for (i = sector / 4; i <= sector_end / 4; i++)
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eccstat[i] = in_be32(&ifc->ifc_nand.nand_eccstat[i]);
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for (i = sector; i <= sector_end; i++) {
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errors = check_read_ecc(mtd, ctrl, eccstat, i);
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if (errors == 15) {
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/*
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* Uncorrectable error.
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* OK only if the whole page is blank.
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*
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* We disable ECCER reporting due to...
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* erratum IFC-A002770 -- so report it now if we
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* see an uncorrectable error in ECCSTAT.
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*/
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if (!is_blank(mtd, bufnum))
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ctrl->nand_stat |=
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IFC_NAND_EVTER_STAT_ECCER;
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break;
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}
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mtd->ecc_stats.corrected += errors;
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nctrl->max_bitflips = max_t(unsigned int,
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nctrl->max_bitflips,
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errors);
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}
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nctrl->eccread = 0;
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}
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}
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static void fsl_ifc_do_read(struct nand_chip *chip,
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int oob,
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struct mtd_info *mtd)
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{
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struct fsl_ifc_mtd *priv = chip->priv;
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struct fsl_ifc_ctrl *ctrl = priv->ctrl;
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struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
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/* Program FIR/IFC_NAND_FCR0 for Small/Large page */
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if (mtd->writesize > 512) {
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out_be32(&ifc->ifc_nand.nand_fir0,
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(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
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(IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
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(IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
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(IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
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(IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT));
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out_be32(&ifc->ifc_nand.nand_fir1, 0x0);
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out_be32(&ifc->ifc_nand.nand_fcr0,
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(NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
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(NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT));
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} else {
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out_be32(&ifc->ifc_nand.nand_fir0,
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(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
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(IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
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(IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
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(IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT));
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out_be32(&ifc->ifc_nand.nand_fir1, 0x0);
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if (oob)
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out_be32(&ifc->ifc_nand.nand_fcr0,
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NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT);
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else
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out_be32(&ifc->ifc_nand.nand_fcr0,
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NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT);
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}
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}
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/* cmdfunc send commands to the IFC NAND Machine */
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static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
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int column, int page_addr) {
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struct nand_chip *chip = mtd->priv;
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struct fsl_ifc_mtd *priv = chip->priv;
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struct fsl_ifc_ctrl *ctrl = priv->ctrl;
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struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
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/* clear the read buffer */
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ifc_nand_ctrl->read_bytes = 0;
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if (command != NAND_CMD_PAGEPROG)
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ifc_nand_ctrl->index = 0;
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switch (command) {
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/* READ0 read the entire buffer to use hardware ECC. */
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case NAND_CMD_READ0:
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out_be32(&ifc->ifc_nand.nand_fbcr, 0);
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set_addr(mtd, 0, page_addr, 0);
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ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
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ifc_nand_ctrl->index += column;
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if (chip->ecc.mode == NAND_ECC_HW)
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ifc_nand_ctrl->eccread = 1;
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fsl_ifc_do_read(chip, 0, mtd);
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fsl_ifc_run_command(mtd);
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return;
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/* READOOB reads only the OOB because no ECC is performed. */
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case NAND_CMD_READOOB:
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out_be32(&ifc->ifc_nand.nand_fbcr, mtd->oobsize - column);
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set_addr(mtd, column, page_addr, 1);
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ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
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fsl_ifc_do_read(chip, 1, mtd);
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fsl_ifc_run_command(mtd);
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return;
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case NAND_CMD_READID:
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case NAND_CMD_PARAM: {
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int timing = IFC_FIR_OP_RB;
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if (command == NAND_CMD_PARAM)
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timing = IFC_FIR_OP_RBCD;
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out_be32(&ifc->ifc_nand.nand_fir0,
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(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
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(IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
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(timing << IFC_NAND_FIR0_OP2_SHIFT));
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out_be32(&ifc->ifc_nand.nand_fcr0,
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command << IFC_NAND_FCR0_CMD0_SHIFT);
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out_be32(&ifc->ifc_nand.row3, column);
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/*
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* although currently it's 8 bytes for READID, we always read
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* the maximum 256 bytes(for PARAM)
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*/
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out_be32(&ifc->ifc_nand.nand_fbcr, 256);
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ifc_nand_ctrl->read_bytes = 256;
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set_addr(mtd, 0, 0, 0);
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fsl_ifc_run_command(mtd);
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return;
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}
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/* ERASE1 stores the block and page address */
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case NAND_CMD_ERASE1:
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set_addr(mtd, 0, page_addr, 0);
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return;
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/* ERASE2 uses the block and page address from ERASE1 */
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case NAND_CMD_ERASE2:
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out_be32(&ifc->ifc_nand.nand_fir0,
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(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
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(IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) |
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(IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT));
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|
|
out_be32(&ifc->ifc_nand.nand_fcr0,
|
|
(NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) |
|
|
(NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT));
|
|
|
|
out_be32(&ifc->ifc_nand.nand_fbcr, 0);
|
|
ifc_nand_ctrl->read_bytes = 0;
|
|
fsl_ifc_run_command(mtd);
|
|
return;
|
|
|
|
/* SEQIN sets up the addr buffer and all registers except the length */
|
|
case NAND_CMD_SEQIN: {
|
|
u32 nand_fcr0;
|
|
ifc_nand_ctrl->column = column;
|
|
ifc_nand_ctrl->oob = 0;
|
|
|
|
if (mtd->writesize > 512) {
|
|
nand_fcr0 =
|
|
(NAND_CMD_SEQIN << IFC_NAND_FCR0_CMD0_SHIFT) |
|
|
(NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD1_SHIFT);
|
|
|
|
out_be32(&ifc->ifc_nand.nand_fir0,
|
|
(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
|
|
(IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
|
|
(IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
|
|
(IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP3_SHIFT) |
|
|
(IFC_FIR_OP_CW1 << IFC_NAND_FIR0_OP4_SHIFT));
|
|
} else {
|
|
nand_fcr0 = ((NAND_CMD_PAGEPROG <<
|
|
IFC_NAND_FCR0_CMD1_SHIFT) |
|
|
(NAND_CMD_SEQIN <<
|
|
IFC_NAND_FCR0_CMD2_SHIFT));
|
|
|
|
out_be32(&ifc->ifc_nand.nand_fir0,
|
|
(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
|
|
(IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) |
|
|
(IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) |
|
|
(IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) |
|
|
(IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT));
|
|
out_be32(&ifc->ifc_nand.nand_fir1,
|
|
(IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT));
|
|
|
|
if (column >= mtd->writesize)
|
|
nand_fcr0 |=
|
|
NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT;
|
|
else
|
|
nand_fcr0 |=
|
|
NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT;
|
|
}
|
|
|
|
if (column >= mtd->writesize) {
|
|
/* OOB area --> READOOB */
|
|
column -= mtd->writesize;
|
|
ifc_nand_ctrl->oob = 1;
|
|
}
|
|
out_be32(&ifc->ifc_nand.nand_fcr0, nand_fcr0);
|
|
set_addr(mtd, column, page_addr, ifc_nand_ctrl->oob);
|
|
return;
|
|
}
|
|
|
|
/* PAGEPROG reuses all of the setup from SEQIN and adds the length */
|
|
case NAND_CMD_PAGEPROG: {
|
|
if (ifc_nand_ctrl->oob) {
|
|
out_be32(&ifc->ifc_nand.nand_fbcr,
|
|
ifc_nand_ctrl->index - ifc_nand_ctrl->column);
|
|
} else {
|
|
out_be32(&ifc->ifc_nand.nand_fbcr, 0);
|
|
}
|
|
|
|
fsl_ifc_run_command(mtd);
|
|
return;
|
|
}
|
|
|
|
case NAND_CMD_STATUS:
|
|
out_be32(&ifc->ifc_nand.nand_fir0,
|
|
(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
|
|
(IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT));
|
|
out_be32(&ifc->ifc_nand.nand_fcr0,
|
|
NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT);
|
|
out_be32(&ifc->ifc_nand.nand_fbcr, 1);
|
|
set_addr(mtd, 0, 0, 0);
|
|
ifc_nand_ctrl->read_bytes = 1;
|
|
|
|
fsl_ifc_run_command(mtd);
|
|
|
|
/*
|
|
* The chip always seems to report that it is
|
|
* write-protected, even when it is not.
|
|
*/
|
|
setbits8(ifc_nand_ctrl->addr, NAND_STATUS_WP);
|
|
return;
|
|
|
|
case NAND_CMD_RESET:
|
|
out_be32(&ifc->ifc_nand.nand_fir0,
|
|
IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT);
|
|
out_be32(&ifc->ifc_nand.nand_fcr0,
|
|
NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT);
|
|
fsl_ifc_run_command(mtd);
|
|
return;
|
|
|
|
default:
|
|
dev_err(priv->dev, "%s: error, unsupported command 0x%x.\n",
|
|
__func__, command);
|
|
}
|
|
}
|
|
|
|
static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip)
|
|
{
|
|
/* The hardware does not seem to support multiple
|
|
* chips per bank.
|
|
*/
|
|
}
|
|
|
|
/*
|
|
* Write buf to the IFC NAND Controller Data Buffer
|
|
*/
|
|
static void fsl_ifc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
|
|
{
|
|
struct nand_chip *chip = mtd->priv;
|
|
struct fsl_ifc_mtd *priv = chip->priv;
|
|
unsigned int bufsize = mtd->writesize + mtd->oobsize;
|
|
|
|
if (len <= 0) {
|
|
dev_err(priv->dev, "%s: len %d bytes", __func__, len);
|
|
return;
|
|
}
|
|
|
|
if ((unsigned int)len > bufsize - ifc_nand_ctrl->index) {
|
|
dev_err(priv->dev,
|
|
"%s: beyond end of buffer (%d requested, %u available)\n",
|
|
__func__, len, bufsize - ifc_nand_ctrl->index);
|
|
len = bufsize - ifc_nand_ctrl->index;
|
|
}
|
|
|
|
memcpy_toio(&ifc_nand_ctrl->addr[ifc_nand_ctrl->index], buf, len);
|
|
ifc_nand_ctrl->index += len;
|
|
}
|
|
|
|
/*
|
|
* Read a byte from either the IFC hardware buffer
|
|
* read function for 8-bit buswidth
|
|
*/
|
|
static uint8_t fsl_ifc_read_byte(struct mtd_info *mtd)
|
|
{
|
|
struct nand_chip *chip = mtd->priv;
|
|
struct fsl_ifc_mtd *priv = chip->priv;
|
|
|
|
/*
|
|
* If there are still bytes in the IFC buffer, then use the
|
|
* next byte.
|
|
*/
|
|
if (ifc_nand_ctrl->index < ifc_nand_ctrl->read_bytes)
|
|
return in_8(&ifc_nand_ctrl->addr[ifc_nand_ctrl->index++]);
|
|
|
|
dev_err(priv->dev, "%s: beyond end of buffer\n", __func__);
|
|
return ERR_BYTE;
|
|
}
|
|
|
|
/*
|
|
* Read two bytes from the IFC hardware buffer
|
|
* read function for 16-bit buswith
|
|
*/
|
|
static uint8_t fsl_ifc_read_byte16(struct mtd_info *mtd)
|
|
{
|
|
struct nand_chip *chip = mtd->priv;
|
|
struct fsl_ifc_mtd *priv = chip->priv;
|
|
uint16_t data;
|
|
|
|
/*
|
|
* If there are still bytes in the IFC buffer, then use the
|
|
* next byte.
|
|
*/
|
|
if (ifc_nand_ctrl->index < ifc_nand_ctrl->read_bytes) {
|
|
data = in_be16((uint16_t __iomem *)&ifc_nand_ctrl->
|
|
addr[ifc_nand_ctrl->index]);
|
|
ifc_nand_ctrl->index += 2;
|
|
return (uint8_t) data;
|
|
}
|
|
|
|
dev_err(priv->dev, "%s: beyond end of buffer\n", __func__);
|
|
return ERR_BYTE;
|
|
}
|
|
|
|
/*
|
|
* Read from the IFC Controller Data Buffer
|
|
*/
|
|
static void fsl_ifc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
|
|
{
|
|
struct nand_chip *chip = mtd->priv;
|
|
struct fsl_ifc_mtd *priv = chip->priv;
|
|
int avail;
|
|
|
|
if (len < 0) {
|
|
dev_err(priv->dev, "%s: len %d bytes", __func__, len);
|
|
return;
|
|
}
|
|
|
|
avail = min((unsigned int)len,
|
|
ifc_nand_ctrl->read_bytes - ifc_nand_ctrl->index);
|
|
memcpy_fromio(buf, &ifc_nand_ctrl->addr[ifc_nand_ctrl->index], avail);
|
|
ifc_nand_ctrl->index += avail;
|
|
|
|
if (len > avail)
|
|
dev_err(priv->dev,
|
|
"%s: beyond end of buffer (%d requested, %d available)\n",
|
|
__func__, len, avail);
|
|
}
|
|
|
|
/*
|
|
* This function is called after Program and Erase Operations to
|
|
* check for success or failure.
|
|
*/
|
|
static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip)
|
|
{
|
|
struct fsl_ifc_mtd *priv = chip->priv;
|
|
struct fsl_ifc_ctrl *ctrl = priv->ctrl;
|
|
struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
|
|
u32 nand_fsr;
|
|
|
|
/* Use READ_STATUS command, but wait for the device to be ready */
|
|
out_be32(&ifc->ifc_nand.nand_fir0,
|
|
(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
|
|
(IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT));
|
|
out_be32(&ifc->ifc_nand.nand_fcr0, NAND_CMD_STATUS <<
|
|
IFC_NAND_FCR0_CMD0_SHIFT);
|
|
out_be32(&ifc->ifc_nand.nand_fbcr, 1);
|
|
set_addr(mtd, 0, 0, 0);
|
|
ifc_nand_ctrl->read_bytes = 1;
|
|
|
|
fsl_ifc_run_command(mtd);
|
|
|
|
nand_fsr = in_be32(&ifc->ifc_nand.nand_fsr);
|
|
|
|
/*
|
|
* The chip always seems to report that it is
|
|
* write-protected, even when it is not.
|
|
*/
|
|
return nand_fsr | NAND_STATUS_WP;
|
|
}
|
|
|
|
static int fsl_ifc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
|
|
uint8_t *buf, int oob_required, int page)
|
|
{
|
|
struct fsl_ifc_mtd *priv = chip->priv;
|
|
struct fsl_ifc_ctrl *ctrl = priv->ctrl;
|
|
struct fsl_ifc_nand_ctrl *nctrl = ifc_nand_ctrl;
|
|
|
|
fsl_ifc_read_buf(mtd, buf, mtd->writesize);
|
|
if (oob_required)
|
|
fsl_ifc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
|
|
|
|
if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_ECCER)
|
|
dev_err(priv->dev, "NAND Flash ECC Uncorrectable Error\n");
|
|
|
|
if (ctrl->nand_stat != IFC_NAND_EVTER_STAT_OPC)
|
|
mtd->ecc_stats.failed++;
|
|
|
|
return nctrl->max_bitflips;
|
|
}
|
|
|
|
/* ECC will be calculated automatically, and errors will be detected in
|
|
* waitfunc.
|
|
*/
|
|
static int fsl_ifc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
|
|
const uint8_t *buf, int oob_required)
|
|
{
|
|
fsl_ifc_write_buf(mtd, buf, mtd->writesize);
|
|
fsl_ifc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int fsl_ifc_chip_init_tail(struct mtd_info *mtd)
|
|
{
|
|
struct nand_chip *chip = mtd->priv;
|
|
struct fsl_ifc_mtd *priv = chip->priv;
|
|
|
|
dev_dbg(priv->dev, "%s: nand->numchips = %d\n", __func__,
|
|
chip->numchips);
|
|
dev_dbg(priv->dev, "%s: nand->chipsize = %lld\n", __func__,
|
|
chip->chipsize);
|
|
dev_dbg(priv->dev, "%s: nand->pagemask = %8x\n", __func__,
|
|
chip->pagemask);
|
|
dev_dbg(priv->dev, "%s: nand->chip_delay = %d\n", __func__,
|
|
chip->chip_delay);
|
|
dev_dbg(priv->dev, "%s: nand->badblockpos = %d\n", __func__,
|
|
chip->badblockpos);
|
|
dev_dbg(priv->dev, "%s: nand->chip_shift = %d\n", __func__,
|
|
chip->chip_shift);
|
|
dev_dbg(priv->dev, "%s: nand->page_shift = %d\n", __func__,
|
|
chip->page_shift);
|
|
dev_dbg(priv->dev, "%s: nand->phys_erase_shift = %d\n", __func__,
|
|
chip->phys_erase_shift);
|
|
dev_dbg(priv->dev, "%s: nand->ecclayout = %p\n", __func__,
|
|
chip->ecclayout);
|
|
dev_dbg(priv->dev, "%s: nand->ecc.mode = %d\n", __func__,
|
|
chip->ecc.mode);
|
|
dev_dbg(priv->dev, "%s: nand->ecc.steps = %d\n", __func__,
|
|
chip->ecc.steps);
|
|
dev_dbg(priv->dev, "%s: nand->ecc.bytes = %d\n", __func__,
|
|
chip->ecc.bytes);
|
|
dev_dbg(priv->dev, "%s: nand->ecc.total = %d\n", __func__,
|
|
chip->ecc.total);
|
|
dev_dbg(priv->dev, "%s: nand->ecc.layout = %p\n", __func__,
|
|
chip->ecc.layout);
|
|
dev_dbg(priv->dev, "%s: mtd->flags = %08x\n", __func__, mtd->flags);
|
|
dev_dbg(priv->dev, "%s: mtd->size = %lld\n", __func__, mtd->size);
|
|
dev_dbg(priv->dev, "%s: mtd->erasesize = %d\n", __func__,
|
|
mtd->erasesize);
|
|
dev_dbg(priv->dev, "%s: mtd->writesize = %d\n", __func__,
|
|
mtd->writesize);
|
|
dev_dbg(priv->dev, "%s: mtd->oobsize = %d\n", __func__,
|
|
mtd->oobsize);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void fsl_ifc_sram_init(struct fsl_ifc_mtd *priv)
|
|
{
|
|
struct fsl_ifc_ctrl *ctrl = priv->ctrl;
|
|
struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
|
|
uint32_t csor = 0, csor_8k = 0, csor_ext = 0;
|
|
uint32_t cs = priv->bank;
|
|
|
|
/* Save CSOR and CSOR_ext */
|
|
csor = in_be32(&ifc->csor_cs[cs].csor);
|
|
csor_ext = in_be32(&ifc->csor_cs[cs].csor_ext);
|
|
|
|
/* chage PageSize 8K and SpareSize 1K*/
|
|
csor_8k = (csor & ~(CSOR_NAND_PGS_MASK)) | 0x0018C000;
|
|
out_be32(&ifc->csor_cs[cs].csor, csor_8k);
|
|
out_be32(&ifc->csor_cs[cs].csor_ext, 0x0000400);
|
|
|
|
/* READID */
|
|
out_be32(&ifc->ifc_nand.nand_fir0,
|
|
(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
|
|
(IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
|
|
(IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT));
|
|
out_be32(&ifc->ifc_nand.nand_fcr0,
|
|
NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT);
|
|
out_be32(&ifc->ifc_nand.row3, 0x0);
|
|
|
|
out_be32(&ifc->ifc_nand.nand_fbcr, 0x0);
|
|
|
|
/* Program ROW0/COL0 */
|
|
out_be32(&ifc->ifc_nand.row0, 0x0);
|
|
out_be32(&ifc->ifc_nand.col0, 0x0);
|
|
|
|
/* set the chip select for NAND Transaction */
|
|
out_be32(&ifc->ifc_nand.nand_csel, cs << IFC_NAND_CSEL_SHIFT);
|
|
|
|
/* start read seq */
|
|
out_be32(&ifc->ifc_nand.nandseq_strt, IFC_NAND_SEQ_STRT_FIR_STRT);
|
|
|
|
/* wait for command complete flag or timeout */
|
|
wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat,
|
|
IFC_TIMEOUT_MSECS * HZ/1000);
|
|
|
|
if (ctrl->nand_stat != IFC_NAND_EVTER_STAT_OPC)
|
|
printk(KERN_ERR "fsl-ifc: Failed to Initialise SRAM\n");
|
|
|
|
/* Restore CSOR and CSOR_ext */
|
|
out_be32(&ifc->csor_cs[cs].csor, csor);
|
|
out_be32(&ifc->csor_cs[cs].csor_ext, csor_ext);
|
|
}
|
|
|
|
static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
|
|
{
|
|
struct fsl_ifc_ctrl *ctrl = priv->ctrl;
|
|
struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
|
|
struct nand_chip *chip = &priv->chip;
|
|
struct nand_ecclayout *layout;
|
|
u32 csor, ver;
|
|
|
|
/* Fill in fsl_ifc_mtd structure */
|
|
priv->mtd.priv = chip;
|
|
priv->mtd.owner = THIS_MODULE;
|
|
|
|
/* fill in nand_chip structure */
|
|
/* set up function call table */
|
|
if ((in_be32(&ifc->cspr_cs[priv->bank].cspr)) & CSPR_PORT_SIZE_16)
|
|
chip->read_byte = fsl_ifc_read_byte16;
|
|
else
|
|
chip->read_byte = fsl_ifc_read_byte;
|
|
|
|
chip->write_buf = fsl_ifc_write_buf;
|
|
chip->read_buf = fsl_ifc_read_buf;
|
|
chip->select_chip = fsl_ifc_select_chip;
|
|
chip->cmdfunc = fsl_ifc_cmdfunc;
|
|
chip->waitfunc = fsl_ifc_wait;
|
|
|
|
chip->bbt_td = &bbt_main_descr;
|
|
chip->bbt_md = &bbt_mirror_descr;
|
|
|
|
out_be32(&ifc->ifc_nand.ncfgr, 0x0);
|
|
|
|
/* set up nand options */
|
|
chip->bbt_options = NAND_BBT_USE_FLASH;
|
|
|
|
|
|
if (in_be32(&ifc->cspr_cs[priv->bank].cspr) & CSPR_PORT_SIZE_16) {
|
|
chip->read_byte = fsl_ifc_read_byte16;
|
|
chip->options |= NAND_BUSWIDTH_16;
|
|
} else {
|
|
chip->read_byte = fsl_ifc_read_byte;
|
|
}
|
|
|
|
chip->controller = &ifc_nand_ctrl->controller;
|
|
chip->priv = priv;
|
|
|
|
chip->ecc.read_page = fsl_ifc_read_page;
|
|
chip->ecc.write_page = fsl_ifc_write_page;
|
|
|
|
csor = in_be32(&ifc->csor_cs[priv->bank].csor);
|
|
|
|
/* Hardware generates ECC per 512 Bytes */
|
|
chip->ecc.size = 512;
|
|
chip->ecc.bytes = 8;
|
|
chip->ecc.strength = 4;
|
|
|
|
switch (csor & CSOR_NAND_PGS_MASK) {
|
|
case CSOR_NAND_PGS_512:
|
|
if (chip->options & NAND_BUSWIDTH_16) {
|
|
layout = &oob_512_16bit_ecc4;
|
|
} else {
|
|
layout = &oob_512_8bit_ecc4;
|
|
|
|
/* Avoid conflict with bad block marker */
|
|
bbt_main_descr.offs = 0;
|
|
bbt_mirror_descr.offs = 0;
|
|
}
|
|
|
|
priv->bufnum_mask = 15;
|
|
break;
|
|
|
|
case CSOR_NAND_PGS_2K:
|
|
layout = &oob_2048_ecc4;
|
|
priv->bufnum_mask = 3;
|
|
break;
|
|
|
|
case CSOR_NAND_PGS_4K:
|
|
if ((csor & CSOR_NAND_ECC_MODE_MASK) ==
|
|
CSOR_NAND_ECC_MODE_4) {
|
|
layout = &oob_4096_ecc4;
|
|
} else {
|
|
layout = &oob_4096_ecc8;
|
|
chip->ecc.bytes = 16;
|
|
}
|
|
|
|
priv->bufnum_mask = 1;
|
|
break;
|
|
|
|
default:
|
|
dev_err(priv->dev, "bad csor %#x: bad page size\n", csor);
|
|
return -ENODEV;
|
|
}
|
|
|
|
/* Must also set CSOR_NAND_ECC_ENC_EN if DEC_EN set */
|
|
if (csor & CSOR_NAND_ECC_DEC_EN) {
|
|
chip->ecc.mode = NAND_ECC_HW;
|
|
chip->ecc.layout = layout;
|
|
} else {
|
|
chip->ecc.mode = NAND_ECC_SOFT;
|
|
}
|
|
|
|
ver = in_be32(&ifc->ifc_rev);
|
|
if (ver == FSL_IFC_V1_1_0)
|
|
fsl_ifc_sram_init(priv);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int fsl_ifc_chip_remove(struct fsl_ifc_mtd *priv)
|
|
{
|
|
nand_release(&priv->mtd);
|
|
|
|
kfree(priv->mtd.name);
|
|
|
|
if (priv->vbase)
|
|
iounmap(priv->vbase);
|
|
|
|
ifc_nand_ctrl->chips[priv->bank] = NULL;
|
|
dev_set_drvdata(priv->dev, NULL);
|
|
kfree(priv);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int match_bank(struct fsl_ifc_regs __iomem *ifc, int bank,
|
|
phys_addr_t addr)
|
|
{
|
|
u32 cspr = in_be32(&ifc->cspr_cs[bank].cspr);
|
|
|
|
if (!(cspr & CSPR_V))
|
|
return 0;
|
|
if ((cspr & CSPR_MSEL) != CSPR_MSEL_NAND)
|
|
return 0;
|
|
|
|
return (cspr & CSPR_BA) == convert_ifc_address(addr);
|
|
}
|
|
|
|
static DEFINE_MUTEX(fsl_ifc_nand_mutex);
|
|
|
|
static int __devinit fsl_ifc_nand_probe(struct platform_device *dev)
|
|
{
|
|
struct fsl_ifc_regs __iomem *ifc;
|
|
struct fsl_ifc_mtd *priv;
|
|
struct resource res;
|
|
static const char *part_probe_types[]
|
|
= { "cmdlinepart", "RedBoot", "ofpart", NULL };
|
|
int ret;
|
|
int bank;
|
|
struct device_node *node = dev->dev.of_node;
|
|
struct mtd_part_parser_data ppdata;
|
|
|
|
ppdata.of_node = dev->dev.of_node;
|
|
if (!fsl_ifc_ctrl_dev || !fsl_ifc_ctrl_dev->regs)
|
|
return -ENODEV;
|
|
ifc = fsl_ifc_ctrl_dev->regs;
|
|
|
|
/* get, allocate and map the memory resource */
|
|
ret = of_address_to_resource(node, 0, &res);
|
|
if (ret) {
|
|
dev_err(&dev->dev, "%s: failed to get resource\n", __func__);
|
|
return ret;
|
|
}
|
|
|
|
/* find which chip select it is connected to */
|
|
for (bank = 0; bank < FSL_IFC_BANK_COUNT; bank++) {
|
|
if (match_bank(ifc, bank, res.start))
|
|
break;
|
|
}
|
|
|
|
if (bank >= FSL_IFC_BANK_COUNT) {
|
|
dev_err(&dev->dev, "%s: address did not match any chip selects\n",
|
|
__func__);
|
|
return -ENODEV;
|
|
}
|
|
|
|
priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
|
|
if (!priv)
|
|
return -ENOMEM;
|
|
|
|
mutex_lock(&fsl_ifc_nand_mutex);
|
|
if (!fsl_ifc_ctrl_dev->nand) {
|
|
ifc_nand_ctrl = kzalloc(sizeof(*ifc_nand_ctrl), GFP_KERNEL);
|
|
if (!ifc_nand_ctrl) {
|
|
dev_err(&dev->dev, "failed to allocate memory\n");
|
|
mutex_unlock(&fsl_ifc_nand_mutex);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
ifc_nand_ctrl->read_bytes = 0;
|
|
ifc_nand_ctrl->index = 0;
|
|
ifc_nand_ctrl->addr = NULL;
|
|
fsl_ifc_ctrl_dev->nand = ifc_nand_ctrl;
|
|
|
|
spin_lock_init(&ifc_nand_ctrl->controller.lock);
|
|
init_waitqueue_head(&ifc_nand_ctrl->controller.wq);
|
|
} else {
|
|
ifc_nand_ctrl = fsl_ifc_ctrl_dev->nand;
|
|
}
|
|
mutex_unlock(&fsl_ifc_nand_mutex);
|
|
|
|
ifc_nand_ctrl->chips[bank] = priv;
|
|
priv->bank = bank;
|
|
priv->ctrl = fsl_ifc_ctrl_dev;
|
|
priv->dev = &dev->dev;
|
|
|
|
priv->vbase = ioremap(res.start, resource_size(&res));
|
|
if (!priv->vbase) {
|
|
dev_err(priv->dev, "%s: failed to map chip region\n", __func__);
|
|
ret = -ENOMEM;
|
|
goto err;
|
|
}
|
|
|
|
dev_set_drvdata(priv->dev, priv);
|
|
|
|
out_be32(&ifc->ifc_nand.nand_evter_en,
|
|
IFC_NAND_EVTER_EN_OPC_EN |
|
|
IFC_NAND_EVTER_EN_FTOER_EN |
|
|
IFC_NAND_EVTER_EN_WPER_EN);
|
|
|
|
/* enable NAND Machine Interrupts */
|
|
out_be32(&ifc->ifc_nand.nand_evter_intr_en,
|
|
IFC_NAND_EVTER_INTR_OPCIR_EN |
|
|
IFC_NAND_EVTER_INTR_FTOERIR_EN |
|
|
IFC_NAND_EVTER_INTR_WPERIR_EN);
|
|
|
|
priv->mtd.name = kasprintf(GFP_KERNEL, "%x.flash", (unsigned)res.start);
|
|
if (!priv->mtd.name) {
|
|
ret = -ENOMEM;
|
|
goto err;
|
|
}
|
|
|
|
ret = fsl_ifc_chip_init(priv);
|
|
if (ret)
|
|
goto err;
|
|
|
|
ret = nand_scan_ident(&priv->mtd, 1, NULL);
|
|
if (ret)
|
|
goto err;
|
|
|
|
ret = fsl_ifc_chip_init_tail(&priv->mtd);
|
|
if (ret)
|
|
goto err;
|
|
|
|
ret = nand_scan_tail(&priv->mtd);
|
|
if (ret)
|
|
goto err;
|
|
|
|
/* First look for RedBoot table or partitions on the command
|
|
* line, these take precedence over device tree information */
|
|
mtd_device_parse_register(&priv->mtd, part_probe_types, &ppdata,
|
|
NULL, 0);
|
|
|
|
dev_info(priv->dev, "IFC NAND device at 0x%llx, bank %d\n",
|
|
(unsigned long long)res.start, priv->bank);
|
|
return 0;
|
|
|
|
err:
|
|
fsl_ifc_chip_remove(priv);
|
|
return ret;
|
|
}
|
|
|
|
static int fsl_ifc_nand_remove(struct platform_device *dev)
|
|
{
|
|
struct fsl_ifc_mtd *priv = dev_get_drvdata(&dev->dev);
|
|
|
|
fsl_ifc_chip_remove(priv);
|
|
|
|
mutex_lock(&fsl_ifc_nand_mutex);
|
|
ifc_nand_ctrl->counter--;
|
|
if (!ifc_nand_ctrl->counter) {
|
|
fsl_ifc_ctrl_dev->nand = NULL;
|
|
kfree(ifc_nand_ctrl);
|
|
}
|
|
mutex_unlock(&fsl_ifc_nand_mutex);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id fsl_ifc_nand_match[] = {
|
|
{
|
|
.compatible = "fsl,ifc-nand",
|
|
},
|
|
{}
|
|
};
|
|
|
|
static struct platform_driver fsl_ifc_nand_driver = {
|
|
.driver = {
|
|
.name = "fsl,ifc-nand",
|
|
.owner = THIS_MODULE,
|
|
.of_match_table = fsl_ifc_nand_match,
|
|
},
|
|
.probe = fsl_ifc_nand_probe,
|
|
.remove = fsl_ifc_nand_remove,
|
|
};
|
|
|
|
static int __init fsl_ifc_nand_init(void)
|
|
{
|
|
int ret;
|
|
|
|
ret = platform_driver_register(&fsl_ifc_nand_driver);
|
|
if (ret)
|
|
printk(KERN_ERR "fsl-ifc: Failed to register platform"
|
|
"driver\n");
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void __exit fsl_ifc_nand_exit(void)
|
|
{
|
|
platform_driver_unregister(&fsl_ifc_nand_driver);
|
|
}
|
|
|
|
module_init(fsl_ifc_nand_init);
|
|
module_exit(fsl_ifc_nand_exit);
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_AUTHOR("Freescale");
|
|
MODULE_DESCRIPTION("Freescale Integrated Flash Controller MTD NAND driver");
|