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818b40e500
Some drivers require direct access to the autoidle functionality of the interface clocks. Added clock APIs for these, so that the drivers do not need to access CM registers directly. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
470 lines
16 KiB
C
470 lines
16 KiB
C
/*
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* linux/arch/arm/mach-omap2/clock.h
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*
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* Copyright (C) 2005-2009 Texas Instruments, Inc.
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* Copyright (C) 2004-2011 Nokia Corporation
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*
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* Contacts:
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* Richard Woodruff <r-woodruff2@ti.com>
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* Paul Walmsley
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H
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#define __ARCH_ARM_MACH_OMAP2_CLOCK_H
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/clkdev.h>
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#include <linux/clk-provider.h>
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struct omap_clk {
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u16 cpu;
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struct clk_lookup lk;
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};
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#define CLK(dev, con, ck) \
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{ \
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.lk = { \
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.dev_id = dev, \
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.con_id = con, \
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.clk = ck, \
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}, \
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}
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struct clockdomain;
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#define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw)
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#define DEFINE_STRUCT_CLK(_name, _parent_array_name, _clkops_name) \
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static struct clk _name = { \
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.name = #_name, \
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.hw = &_name##_hw.hw, \
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.parent_names = _parent_array_name, \
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.num_parents = ARRAY_SIZE(_parent_array_name), \
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.ops = &_clkops_name, \
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};
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#define DEFINE_STRUCT_CLK_FLAGS(_name, _parent_array_name, \
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_clkops_name, _flags) \
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static struct clk _name = { \
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.name = #_name, \
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.hw = &_name##_hw.hw, \
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.parent_names = _parent_array_name, \
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.num_parents = ARRAY_SIZE(_parent_array_name), \
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.ops = &_clkops_name, \
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.flags = _flags, \
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};
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#define DEFINE_STRUCT_CLK_HW_OMAP(_name, _clkdm_name) \
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static struct clk_hw_omap _name##_hw = { \
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.hw = { \
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.clk = &_name, \
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}, \
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.clkdm_name = _clkdm_name, \
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};
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#define DEFINE_CLK_OMAP_MUX(_name, _clkdm_name, _clksel, \
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_clksel_reg, _clksel_mask, \
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_parent_names, _ops) \
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static struct clk _name; \
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static struct clk_hw_omap _name##_hw = { \
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.hw = { \
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.clk = &_name, \
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}, \
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.clksel = _clksel, \
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.clksel_reg = _clksel_reg, \
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.clksel_mask = _clksel_mask, \
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.clkdm_name = _clkdm_name, \
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}; \
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DEFINE_STRUCT_CLK(_name, _parent_names, _ops);
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#define DEFINE_CLK_OMAP_MUX_GATE(_name, _clkdm_name, _clksel, \
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_clksel_reg, _clksel_mask, \
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_enable_reg, _enable_bit, \
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_hwops, _parent_names, _ops) \
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static struct clk _name; \
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static struct clk_hw_omap _name##_hw = { \
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.hw = { \
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.clk = &_name, \
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}, \
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.ops = _hwops, \
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.enable_reg = _enable_reg, \
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.enable_bit = _enable_bit, \
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.clksel = _clksel, \
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.clksel_reg = _clksel_reg, \
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.clksel_mask = _clksel_mask, \
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.clkdm_name = _clkdm_name, \
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}; \
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DEFINE_STRUCT_CLK(_name, _parent_names, _ops);
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#define DEFINE_CLK_OMAP_HSDIVIDER(_name, _parent_name, \
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_parent_ptr, _flags, \
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_clksel_reg, _clksel_mask) \
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static const struct clksel _name##_div[] = { \
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{ \
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.parent = _parent_ptr, \
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.rates = div31_1to31_rates \
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}, \
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{ .parent = NULL }, \
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}; \
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static struct clk _name; \
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static const char *_name##_parent_names[] = { \
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_parent_name, \
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}; \
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static struct clk_hw_omap _name##_hw = { \
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.hw = { \
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.clk = &_name, \
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}, \
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.clksel = _name##_div, \
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.clksel_reg = _clksel_reg, \
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.clksel_mask = _clksel_mask, \
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.ops = &clkhwops_omap4_dpllmx, \
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}; \
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DEFINE_STRUCT_CLK(_name, _name##_parent_names, omap_hsdivider_ops);
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/* struct clksel_rate.flags possibilities */
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#define RATE_IN_242X (1 << 0)
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#define RATE_IN_243X (1 << 1)
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#define RATE_IN_3430ES1 (1 << 2) /* 3430ES1 rates only */
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#define RATE_IN_3430ES2PLUS (1 << 3) /* 3430 ES >= 2 rates only */
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#define RATE_IN_36XX (1 << 4)
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#define RATE_IN_4430 (1 << 5)
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#define RATE_IN_TI816X (1 << 6)
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#define RATE_IN_4460 (1 << 7)
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#define RATE_IN_AM33XX (1 << 8)
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#define RATE_IN_TI814X (1 << 9)
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#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X)
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#define RATE_IN_34XX (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS)
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#define RATE_IN_3XXX (RATE_IN_34XX | RATE_IN_36XX)
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#define RATE_IN_44XX (RATE_IN_4430 | RATE_IN_4460)
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/* RATE_IN_3430ES2PLUS_36XX includes 34xx/35xx with ES >=2, and all 36xx/37xx */
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#define RATE_IN_3430ES2PLUS_36XX (RATE_IN_3430ES2PLUS | RATE_IN_36XX)
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/**
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* struct clksel_rate - register bitfield values corresponding to clk divisors
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* @val: register bitfield value (shifted to bit 0)
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* @div: clock divisor corresponding to @val
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* @flags: (see "struct clksel_rate.flags possibilities" above)
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*
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* @val should match the value of a read from struct clk.clksel_reg
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* AND'ed with struct clk.clksel_mask, shifted right to bit 0.
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*
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* @div is the divisor that should be applied to the parent clock's rate
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* to produce the current clock's rate.
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*/
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struct clksel_rate {
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u32 val;
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u8 div;
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u16 flags;
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};
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/**
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* struct clksel - available parent clocks, and a pointer to their divisors
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* @parent: struct clk * to a possible parent clock
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* @rates: available divisors for this parent clock
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*
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* A struct clksel is always associated with one or more struct clks
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* and one or more struct clksel_rates.
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*/
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struct clksel {
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struct clk *parent;
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const struct clksel_rate *rates;
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};
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/**
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* struct dpll_data - DPLL registers and integration data
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* @mult_div1_reg: register containing the DPLL M and N bitfields
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* @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
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* @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
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* @clk_bypass: struct clk pointer to the clock's bypass clock input
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* @clk_ref: struct clk pointer to the clock's reference clock input
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* @control_reg: register containing the DPLL mode bitfield
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* @enable_mask: mask of the DPLL mode bitfield in @control_reg
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* @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate()
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* @last_rounded_m: cache of the last M result of omap2_dpll_round_rate()
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* @last_rounded_m4xen: cache of the last M4X result of
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* omap4_dpll_regm4xen_round_rate()
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* @last_rounded_lpmode: cache of the last lpmode result of
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* omap4_dpll_lpmode_recalc()
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* @max_multiplier: maximum valid non-bypass multiplier value (actual)
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* @last_rounded_n: cache of the last N result of omap2_dpll_round_rate()
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* @min_divider: minimum valid non-bypass divider value (actual)
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* @max_divider: maximum valid non-bypass divider value (actual)
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* @modes: possible values of @enable_mask
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* @autoidle_reg: register containing the DPLL autoidle mode bitfield
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* @idlest_reg: register containing the DPLL idle status bitfield
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* @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
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* @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
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* @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
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* @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg
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* @m4xen_mask: mask of the DPLL M4X multiplier bitfield in @control_reg
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* @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
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* @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs
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* @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs
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* @flags: DPLL type/features (see below)
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*
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* Possible values for @flags:
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* DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
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*
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* @freqsel_mask is only used on the OMAP34xx family and AM35xx.
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*
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* XXX Some DPLLs have multiple bypass inputs, so it's not technically
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* correct to only have one @clk_bypass pointer.
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*
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* XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
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* @last_rounded_n) should be separated from the runtime-fixed fields
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* and placed into a different structure, so that the runtime-fixed data
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* can be placed into read-only space.
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*/
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struct dpll_data {
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void __iomem *mult_div1_reg;
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u32 mult_mask;
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u32 div1_mask;
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struct clk *clk_bypass;
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struct clk *clk_ref;
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void __iomem *control_reg;
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u32 enable_mask;
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unsigned long last_rounded_rate;
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u16 last_rounded_m;
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u8 last_rounded_m4xen;
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u8 last_rounded_lpmode;
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u16 max_multiplier;
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u8 last_rounded_n;
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u8 min_divider;
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u16 max_divider;
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u8 modes;
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void __iomem *autoidle_reg;
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void __iomem *idlest_reg;
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u32 autoidle_mask;
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u32 freqsel_mask;
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u32 idlest_mask;
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u32 dco_mask;
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u32 sddiv_mask;
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u32 lpmode_mask;
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u32 m4xen_mask;
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u8 auto_recal_bit;
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u8 recal_en_bit;
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u8 recal_st_bit;
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u8 flags;
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};
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/*
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* struct clk.flags possibilities
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*
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* XXX document the rest of the clock flags here
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*
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* CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL
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* bits share the same register. This flag allows the
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* omap4_dpllmx*() code to determine which GATE_CTRL bit field
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* should be used. This is a temporary solution - a better approach
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* would be to associate clock type-specific data with the clock,
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* similar to the struct dpll_data approach.
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*/
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#define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */
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#define CLOCK_IDLE_CONTROL (1 << 1)
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#define CLOCK_NO_IDLE_PARENT (1 << 2)
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#define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */
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#define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */
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#define CLOCK_CLKOUTX2 (1 << 5)
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/**
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* struct clk_hw_omap - OMAP struct clk
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* @node: list_head connecting this clock into the full clock list
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* @enable_reg: register to write to enable the clock (see @enable_bit)
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* @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
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* @flags: see "struct clk.flags possibilities" above
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* @clksel_reg: for clksel clks, register va containing src/divisor select
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* @clksel_mask: bitmask in @clksel_reg for the src/divisor selector
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* @clksel: for clksel clks, pointer to struct clksel for this clock
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* @dpll_data: for DPLLs, pointer to struct dpll_data for this clock
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* @clkdm_name: clockdomain name that this clock is contained in
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* @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime
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* @rate_offset: bitshift for rate selection bitfield (OMAP1 only)
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* @src_offset: bitshift for source selection bitfield (OMAP1 only)
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*
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* XXX @rate_offset, @src_offset should probably be removed and OMAP1
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* clock code converted to use clksel.
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*
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*/
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struct clk_hw_omap_ops;
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struct clk_hw_omap {
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struct clk_hw hw;
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struct list_head node;
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unsigned long fixed_rate;
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u8 fixed_div;
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void __iomem *enable_reg;
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u8 enable_bit;
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u8 flags;
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void __iomem *clksel_reg;
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u32 clksel_mask;
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const struct clksel *clksel;
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struct dpll_data *dpll_data;
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const char *clkdm_name;
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struct clockdomain *clkdm;
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const struct clk_hw_omap_ops *ops;
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};
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struct clk_hw_omap_ops {
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void (*find_idlest)(struct clk_hw_omap *oclk,
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void __iomem **idlest_reg,
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u8 *idlest_bit, u8 *idlest_val);
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void (*find_companion)(struct clk_hw_omap *oclk,
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void __iomem **other_reg,
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u8 *other_bit);
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void (*allow_idle)(struct clk_hw_omap *oclk);
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void (*deny_idle)(struct clk_hw_omap *oclk);
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};
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unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw,
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unsigned long parent_rate);
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/* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */
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#define CORE_CLK_SRC_32K 0x0
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#define CORE_CLK_SRC_DPLL 0x1
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#define CORE_CLK_SRC_DPLL_X2 0x2
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/* OMAP2xxx CM_CLKEN_PLL.EN_DPLL bits - for omap2_get_dpll_rate() */
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#define OMAP2XXX_EN_DPLL_LPBYPASS 0x1
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#define OMAP2XXX_EN_DPLL_FRBYPASS 0x2
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#define OMAP2XXX_EN_DPLL_LOCKED 0x3
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/* OMAP3xxx CM_CLKEN_PLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
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#define OMAP3XXX_EN_DPLL_LPBYPASS 0x5
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#define OMAP3XXX_EN_DPLL_FRBYPASS 0x6
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#define OMAP3XXX_EN_DPLL_LOCKED 0x7
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/* OMAP4xxx CM_CLKMODE_DPLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
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#define OMAP4XXX_EN_DPLL_MNBYPASS 0x4
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#define OMAP4XXX_EN_DPLL_LPBYPASS 0x5
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#define OMAP4XXX_EN_DPLL_FRBYPASS 0x6
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#define OMAP4XXX_EN_DPLL_LOCKED 0x7
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/* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
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#define DPLL_LOW_POWER_STOP 0x1
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#define DPLL_LOW_POWER_BYPASS 0x5
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#define DPLL_LOCKED 0x7
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/* DPLL Type and DCO Selection Flags */
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#define DPLL_J_TYPE 0x1
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long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
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unsigned long *parent_rate);
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unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
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int omap3_noncore_dpll_enable(struct clk_hw *hw);
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void omap3_noncore_dpll_disable(struct clk_hw *hw);
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int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate);
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u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk);
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void omap3_dpll_allow_idle(struct clk_hw_omap *clk);
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void omap3_dpll_deny_idle(struct clk_hw_omap *clk);
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unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
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unsigned long parent_rate);
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int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk);
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void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk);
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void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk);
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unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
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unsigned long parent_rate);
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long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
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unsigned long target_rate,
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unsigned long *parent_rate);
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void omap2_init_clk_clkdm(struct clk_hw *clk);
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void __init omap2_clk_disable_clkdm_control(void);
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/* clkt_clksel.c public functions */
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u32 omap2_clksel_round_rate_div(struct clk_hw_omap *clk,
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unsigned long target_rate,
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u32 *new_div);
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u8 omap2_clksel_find_parent_index(struct clk_hw *hw);
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unsigned long omap2_clksel_recalc(struct clk_hw *hw, unsigned long parent_rate);
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long omap2_clksel_round_rate(struct clk_hw *hw, unsigned long target_rate,
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unsigned long *parent_rate);
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int omap2_clksel_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate);
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int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val);
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/* clkt_iclk.c public functions */
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extern void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk);
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extern void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk);
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u8 omap2_init_dpll_parent(struct clk_hw *hw);
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unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk);
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int omap2_dflt_clk_enable(struct clk_hw *hw);
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void omap2_dflt_clk_disable(struct clk_hw *hw);
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int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
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void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
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void __iomem **other_reg,
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u8 *other_bit);
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void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
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void __iomem **idlest_reg,
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u8 *idlest_bit, u8 *idlest_val);
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void omap2_init_clk_hw_omap_clocks(struct clk *clk);
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int omap2_clk_enable_autoidle_all(void);
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int omap2_clk_disable_autoidle_all(void);
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int omap2_clk_allow_idle(struct clk *clk);
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int omap2_clk_deny_idle(struct clk *clk);
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void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
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int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name);
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void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
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const char *core_ck_name,
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const char *mpu_ck_name);
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extern u16 cpu_mask;
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extern const struct clkops clkops_omap2_dflt_wait;
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extern const struct clkops clkops_dummy;
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extern const struct clkops clkops_omap2_dflt;
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extern struct clk_functions omap2_clk_functions;
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extern const struct clksel_rate gpt_32k_rates[];
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extern const struct clksel_rate gpt_sys_rates[];
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extern const struct clksel_rate gfx_l3_rates[];
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extern const struct clksel_rate dsp_ick_rates[];
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extern struct clk dummy_ck;
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extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
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extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
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extern const struct clk_hw_omap_ops clkhwops_wait;
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extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
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extern const struct clk_hw_omap_ops clkhwops_iclk;
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extern const struct clk_hw_omap_ops clkhwops_omap3430es2_ssi_wait;
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extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
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extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait;
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extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait;
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extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait;
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extern const struct clk_hw_omap_ops clkhwops_omap3430es2_hsotgusb_wait;
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extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait;
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extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait;
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extern const struct clk_hw_omap_ops clkhwops_apll54;
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extern const struct clk_hw_omap_ops clkhwops_apll96;
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extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll;
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extern const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait;
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/* clksel_rate blocks shared between OMAP44xx and AM33xx */
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extern const struct clksel_rate div_1_0_rates[];
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extern const struct clksel_rate div3_1to4_rates[];
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extern const struct clksel_rate div_1_1_rates[];
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extern const struct clksel_rate div_1_2_rates[];
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extern const struct clksel_rate div_1_3_rates[];
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extern const struct clksel_rate div_1_4_rates[];
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extern const struct clksel_rate div31_1to31_rates[];
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extern int am33xx_clk_init(void);
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extern int omap2_clkops_enable_clkdm(struct clk_hw *hw);
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extern void omap2_clkops_disable_clkdm(struct clk_hw *hw);
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extern void omap_clocks_register(struct omap_clk *oclks, int cnt);
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#endif
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