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dc37374b9c
It makes no sense that some Freescale device tree files are in fsl directory while some others not. This patch move Freescale device tree files into fsl folder. To do that the following two steps are made: - Move Freescale device tree files into fsl folder. - Update the include path in these files from "fsl/*.dtsi" to "*.dtsi". Please add "fsl/" prefix when you make dtb using Makefile. Signed-off-by: Jia Hongtao <hongtao.jia@freescale.com> [scottwood: fixed cuImage rule] Signed-off-by: Scott Wood <scottwood@freescale.com>
91 lines
2.2 KiB
Plaintext
91 lines
2.2 KiB
Plaintext
/*
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* MPC8572DS Device Tree Source (36-bit address map)
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*
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* Copyright 2007-2009 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/include/ "mpc8572si-pre.dtsi"
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/ {
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model = "fsl,MPC8572DS";
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compatible = "fsl,MPC8572DS";
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memory {
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device_type = "memory";
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};
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board_lbc: lbc: localbus@fffe05000 {
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reg = <0xf 0xffe05000 0 0x1000>;
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ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
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0x1 0x0 0xf 0xe0000000 0x08000000
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0x2 0x0 0xf 0xffa00000 0x00040000
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0x3 0x0 0xf 0xffdf0000 0x00008000
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0x4 0x0 0xf 0xffa40000 0x00040000
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0x5 0x0 0xf 0xffa80000 0x00040000
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0x6 0x0 0xf 0xffac0000 0x00040000>;
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};
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board_soc: soc: soc8572@fffe00000 {
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ranges = <0x0 0xf 0xffe00000 0x100000>;
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};
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board_pci0: pci0: pcie@fffe08000 {
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reg = <0xf 0xffe08000 0 0x1000>;
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ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000
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0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x00010000>;
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pcie@0 {
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ranges = <0x2000000 0x0 0xe0000000
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0x2000000 0x0 0xe0000000
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0x0 0x20000000
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0x1000000 0x0 0x0
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0x1000000 0x0 0x0
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0x0 0x10000>;
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};
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};
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pci1: pcie@fffe09000 {
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reg = <0xf 0xffe09000 0 0x1000>;
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ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
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0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x00010000>;
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pcie@0 {
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ranges = <0x2000000 0x0 0xe0000000
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0x2000000 0x0 0xe0000000
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0x0 0x20000000
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0x1000000 0x0 0x0
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0x1000000 0x0 0x0
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0x0 0x10000>;
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};
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};
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pci2: pcie@fffe0a000 {
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reg = <0xf 0xffe0a000 0 0x1000>;
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ranges = <0x2000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000
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0x1000000 0x0 0x00000000 0xf 0xffc20000 0x0 0x00010000>;
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pcie@0 {
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ranges = <0x2000000 0x0 0xe0000000
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0x2000000 0x0 0xe0000000
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0x0 0x20000000
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0x1000000 0x0 0x0
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0x1000000 0x0 0x0
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0x0 0x10000>;
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};
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};
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};
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/*
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* mpc8572ds.dtsi must be last to ensure board_pci0 overrides pci0 settings
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* for interrupt-map & interrupt-map-mask
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*/
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/include/ "mpc8572si-post.dtsi"
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/include/ "mpc8572ds.dtsi"
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