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Many platforms support simple gateable clocks, fixed-rate clocks, adjustable divider clocks and multi-parent multiplexer clocks. This patch introduces basic clock types for the above-mentioned hardware which share some common characteristics. Based on original work by Jeremy Kerr and contribution by Jamie Iles. Dividers and multiplexor clocks originally contributed by Richard Zhao & Sascha Hauer. Signed-off-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Mike Turquette <mturquette@ti.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Rob Herring <rob.herring@calxeda.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Jeremy Kerr <jeremy.kerr@canonical.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Arnd Bergman <arnd.bergmann@linaro.org> Cc: Paul Walmsley <paul@pwsan.com> Cc: Shawn Guo <shawn.guo@freescale.com> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Jamie Iles <jamie@jamieiles.com> Cc: Richard Zhao <richard.zhao@linaro.org> Cc: Saravana Kannan <skannan@codeaurora.org> Cc: Magnus Damm <magnus.damm@gmail.com> Cc: Mark Brown <broonie@opensource.wolfsonmicro.com> Cc: Linus Walleij <linus.walleij@stericsson.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Amit Kucheria <amit.kucheria@linaro.org> Cc: Deepak Saxena <dsaxena@linaro.org> Cc: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
201 lines
4.7 KiB
C
201 lines
4.7 KiB
C
/*
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* Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
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* Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
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* Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Adjustable divider clock implementation
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*/
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include <linux/string.h>
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/*
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* DOC: basic adjustable divider clock that cannot gate
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*
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* Traits of this clock:
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* prepare - clk_prepare only ensures that parents are prepared
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* enable - clk_enable only ensures that parents are enabled
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* rate - rate is adjustable. clk->rate = parent->rate / divisor
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* parent - fixed parent. No clk_set_parent support
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*/
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#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
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#define div_mask(d) ((1 << (d->width)) - 1)
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static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_divider *divider = to_clk_divider(hw);
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unsigned int div;
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div = readl(divider->reg) >> divider->shift;
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div &= div_mask(divider);
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if (!(divider->flags & CLK_DIVIDER_ONE_BASED))
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div++;
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return parent_rate / div;
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}
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EXPORT_SYMBOL_GPL(clk_divider_recalc_rate);
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/*
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* The reverse of DIV_ROUND_UP: The maximum number which
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* divided by m is r
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*/
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#define MULT_ROUND_UP(r, m) ((r) * (m) + (m) - 1)
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static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
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unsigned long *best_parent_rate)
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{
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struct clk_divider *divider = to_clk_divider(hw);
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int i, bestdiv = 0;
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unsigned long parent_rate, best = 0, now, maxdiv;
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if (!rate)
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rate = 1;
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maxdiv = (1 << divider->width);
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if (divider->flags & CLK_DIVIDER_ONE_BASED)
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maxdiv--;
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if (!best_parent_rate) {
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parent_rate = __clk_get_rate(__clk_get_parent(hw->clk));
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bestdiv = DIV_ROUND_UP(parent_rate, rate);
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bestdiv = bestdiv == 0 ? 1 : bestdiv;
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bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
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return bestdiv;
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}
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/*
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* The maximum divider we can use without overflowing
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* unsigned long in rate * i below
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*/
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maxdiv = min(ULONG_MAX / rate, maxdiv);
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for (i = 1; i <= maxdiv; i++) {
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parent_rate = __clk_round_rate(__clk_get_parent(hw->clk),
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MULT_ROUND_UP(rate, i));
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now = parent_rate / i;
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if (now <= rate && now > best) {
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bestdiv = i;
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best = now;
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*best_parent_rate = parent_rate;
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}
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}
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if (!bestdiv) {
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bestdiv = (1 << divider->width);
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if (divider->flags & CLK_DIVIDER_ONE_BASED)
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bestdiv--;
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*best_parent_rate = __clk_round_rate(__clk_get_parent(hw->clk), 1);
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}
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return bestdiv;
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}
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static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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int div;
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div = clk_divider_bestdiv(hw, rate, prate);
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if (prate)
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return *prate / div;
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else {
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unsigned long r;
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r = __clk_get_rate(__clk_get_parent(hw->clk));
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return r / div;
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}
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}
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EXPORT_SYMBOL_GPL(clk_divider_round_rate);
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static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate)
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{
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struct clk_divider *divider = to_clk_divider(hw);
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unsigned int div;
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unsigned long flags = 0;
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u32 val;
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div = __clk_get_rate(__clk_get_parent(hw->clk)) / rate;
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if (!(divider->flags & CLK_DIVIDER_ONE_BASED))
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div--;
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if (div > div_mask(divider))
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div = div_mask(divider);
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if (divider->lock)
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spin_lock_irqsave(divider->lock, flags);
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val = readl(divider->reg);
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val &= ~(div_mask(divider) << divider->shift);
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val |= div << divider->shift;
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writel(val, divider->reg);
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if (divider->lock)
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spin_unlock_irqrestore(divider->lock, flags);
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return 0;
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}
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EXPORT_SYMBOL_GPL(clk_divider_set_rate);
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struct clk_ops clk_divider_ops = {
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.recalc_rate = clk_divider_recalc_rate,
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.round_rate = clk_divider_round_rate,
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.set_rate = clk_divider_set_rate,
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};
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EXPORT_SYMBOL_GPL(clk_divider_ops);
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struct clk *clk_register_divider(struct device *dev, const char *name,
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const char *parent_name, unsigned long flags,
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void __iomem *reg, u8 shift, u8 width,
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u8 clk_divider_flags, spinlock_t *lock)
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{
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struct clk_divider *div;
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struct clk *clk;
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div = kzalloc(sizeof(struct clk_divider), GFP_KERNEL);
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if (!div) {
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pr_err("%s: could not allocate divider clk\n", __func__);
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return NULL;
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}
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/* struct clk_divider assignments */
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div->reg = reg;
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div->shift = shift;
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div->width = width;
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div->flags = clk_divider_flags;
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div->lock = lock;
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if (parent_name) {
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div->parent[0] = kstrdup(parent_name, GFP_KERNEL);
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if (!div->parent[0])
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goto out;
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}
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clk = clk_register(dev, name,
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&clk_divider_ops, &div->hw,
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div->parent,
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(parent_name ? 1 : 0),
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flags);
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if (clk)
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return clk;
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out:
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kfree(div->parent[0]);
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kfree(div);
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return NULL;
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}
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